公开(公告)号：US20190288830A1

公开(公告)日：2019-09-19

申请号：US15920251

申请日：2018-03-13

Applicant: Xilinx, Inc.

Inventor： Yi Zhuang ,  Winson Lin ,  Jinyung Namkoong ,  Hsung Jai Im ,  Stanley Y. Chen

IPC: H04L7/033 ,  H04L7/00 ,  H03K19/0175 ,  G06F1/06

Abstract: A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.

公开(公告)号：US10484167B2

公开(公告)日：2019-11-19

申请号：US15920251

申请日：2018-03-13

Applicant: Xilinx, Inc.

Inventor： Yi Zhuang ,  Winson Lin ,  Jinyung Namkoong ,  Hsung Jai Im ,  Stanley Y. Chen

IPC: H04L7/00 ,  H04L7/033 ,  G06F1/06 ,  H03K19/0175 ,  H03K19/20

Abstract: A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.