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公开(公告)号：US20190288830A1
公开(公告)日：2019-09-19
申请号：US15920251
申请日：2018-03-13
Applicant: Xilinx, Inc.
Inventor： Yi Zhuang , Winson Lin , Jinyung Namkoong , Hsung Jai Im , Stanley Y. Chen
IPC: H04L7/033 , H04L7/00 , H03K19/0175 , G06F1/06
Abstract: A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.
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公开(公告)号：US09876489B1
公开(公告)日：2018-01-23
申请号：US15258696
申请日：2016-09-07
Applicant: Xilinx, Inc.
Inventor： Ronan Casey , Catherine Hearne , Jinyung Namkoong
CPC classification number: H03K5/05 , H03K5/06 , H03K5/065 , H03K5/135 , H03K5/1515 , H03K2005/00052 , H04L7/0025
Abstract: The phase interpolator comprises a first charge pump configured to receive a first differential clock signal having a first clock phase, wherein the first charge pump has a first current path and a second current path coupled between a first pull-up current source and a first pull-down current source, wherein the first current path comprises a first NMOS steering switch coupled between a first output node and the first pull-down current source and the second current path comprises a second NMOS steering switch coupled between a second output node and the first pull-down current source; and a second charge pump configured to receive a second differential clock signal having a second clock phase, wherein the second charge pump has a third current path and a fourth current path coupled between a second pull-up current source and a second pull-down current source, and wherein the third current path comprises a third NMOS steering switch coupled between the first output node and the second pull-down current source and the fourth current path comprises a fourth NMOS steering switch coupled between the second node and the second pull-down current source.
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公开(公告)号：US20180013435A1
公开(公告)日：2018-01-11
申请号：US15206634
申请日：2016-07-11
Applicant: Xilinx, Inc.
Inventor： Jinyung Namkoong , Mayank Raj , Parag Upadhyaya , Vamshi Manthena , Catherine Hearne , Marc Erett
CPC classification number: H03L7/0891 , H03L7/0805 , H03L7/0995 , H03L7/24 , H03M9/00
Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.
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公开(公告)号：US09667236B1
公开(公告)日：2017-05-30
申请号：US15011012
申请日：2016-01-29
Applicant: Xilinx, Inc.
Inventor： Junho Cho , Jinyung Namkoong
CPC classification number: H03K5/13 , H03K2005/00052 , H03M1/742
Abstract: A phase interpolator includes: a digital-to-analog converter to generate bias signals associated with phase signals; a multiplexer having an input interface and an output interface, wherein the digital-to-analog converter is coupled to the input interface of the multiplexer; a first current source; and a second current source; wherein the digital-to-analog converter is configured to provide bleeder current signals to the first current source and the second current source while bypassing the multiplexer.
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Patent Agency Ranking
公开(公告)号：US09774315B2
公开(公告)日：2017-09-26
申请号：US14933346
申请日：2015-11-05
Applicant: Xilinx, Inc.
Inventor： Jinyung Namkoong , Wenfeng Zhang , Parag Upadhyaya
CPC classification number: H03K3/01 , H03K19/017527
Abstract: Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.
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公开(公告)号：US10536151B1
公开(公告)日：2020-01-14
申请号：US16024473
申请日：2018-06-29
Applicant: Xilinx, Inc.
Inventor： Lei Zhou , Jinyung Namkoong , Stanley Y. Chen , Parag Upadhyaya
Abstract: An injection locked oscillator (ILO) circuit is disclosed. The ILO circuit may include a first clock injection stage including a first programmable inverter in series with a first self-biased inverter. The first injection stage may receive a first input clock having a first frequency and generate a first injection signal. The ILO circuit may further include a second clock injection stage including a second programmable inverter in series with a second self-biased inverter. The second injection stage may receive a second input clock signal having the first frequency and to generate a second injection signal. The ILO may further include a phase locked loop (PLL) stage including a multi-stage ring oscillator. The PLL stage may receive the first injection signal and the second injection signal and to generate an output clock signal based at least in part on the first frequency.
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公开(公告)号：US10484167B2
公开(公告)日：2019-11-19
申请号：US15920251
申请日：2018-03-13
Applicant: Xilinx, Inc.
Inventor： Yi Zhuang , Winson Lin , Jinyung Namkoong , Hsung Jai Im , Stanley Y. Chen
IPC: H04L7/00 , H04L7/033 , G06F1/06 , H03K19/0175 , H03K19/20
Abstract: A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.
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公开(公告)号：US09954539B2
公开(公告)日：2018-04-24
申请号：US15206634
申请日：2016-07-11
Applicant: Xilinx, Inc.
Inventor： Jinyung Namkoong , Mayank Raj , Parag Upadhyaya , Vamshi Manthena , Catherine Hearne , Marc Erett
CPC classification number: H03L7/0891 , H03L7/0805 , H03L7/0995 , H03L7/24 , H03M9/00
Abstract: A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.
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公开(公告)号：US20170134009A1
公开(公告)日：2017-05-11
申请号：US14933346
申请日：2015-11-05
Applicant: Xilinx, Inc.
Inventor： Jinyung Namkoong , Wenfeng Zhang , Parag Upadhyaya
IPC: H03K3/01
CPC classification number: H03K3/01 , H03K19/017527
Abstract: Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.
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