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    Temperature-locked loop for optical elements having a temperature-dependent response
    2.
    发明授权
    Temperature-locked loop for optical elements having a temperature-dependent response 有权

    公开(公告)号：US11005572B1

    公开(公告)日：2021-05-11

    申请号：US17093399

    申请日：2020-11-09

    Applicant: XILINX, INC.

    Inventor： Ping Chuan Chiang ,  Mayank Raj ,  Chuan Xie ,  Stanley Y. Chen ,  Sandeep Kumar ,  Sukruth Pattanagiri ,  Parag Upadhyaya ,  Yohan Frans

    IPC: H04B10/69 ,  H03L1/02 ,  H03L7/189

    Abstract: Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a slicer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the slicer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the slicer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the slicer circuit.

    Circuit for and method of receiving signals in an integrated circuit device
    3.
    发明授权
    Circuit for and method of receiving signals in an integrated circuit device 有权

    公开(公告)号：US10715358B1

    公开(公告)日：2020-07-14

    申请号：US16205020

    申请日：2018-11-29

    Applicant: Xilinx, Inc.

    Inventor： Wenfeng Zhang ,  Stanley Y. Chen ,  Hsung Jai Im ,  Parag Upadhyaya

    IPC: H04L25/03

    Abstract: A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.

    Ultra-low-power injection locked oscillator for IQ clock generation
    4.
    发明授权
    Ultra-low-power injection locked oscillator for IQ clock generation 有权

    公开(公告)号：US10536151B1

    公开(公告)日：2020-01-14

    申请号：US16024473

    申请日：2018-06-29

    Applicant: Xilinx, Inc.

    Inventor： Lei Zhou ,  Jinyung Namkoong ,  Stanley Y. Chen ,  Parag Upadhyaya

    IPC: H03L7/08 ,  G06F1/06 ,  H03K3/03

    Abstract: An injection locked oscillator (ILO) circuit is disclosed. The ILO circuit may include a first clock injection stage including a first programmable inverter in series with a first self-biased inverter. The first injection stage may receive a first input clock having a first frequency and generate a first injection signal. The ILO circuit may further include a second clock injection stage including a second programmable inverter in series with a second self-biased inverter. The second injection stage may receive a second input clock signal having the first frequency and to generate a second injection signal. The ILO may further include a phase locked loop (PLL) stage including a multi-stage ring oscillator. The PLL stage may receive the first injection signal and the second injection signal and to generate an output clock signal based at least in part on the first frequency.

    TRANSMITTER CONFIGURED FOR TEST SIGNAL INJECTION TO TEST AC-COUPLED INTERCONNECT
    6.
    发明申请
    TRANSMITTER CONFIGURED FOR TEST SIGNAL INJECTION TO TEST AC-COUPLED INTERCONNECT 有权
    发射机配置用于测试信号注射到测试交流耦合互连

    公开(公告)号：US20160341780A1

    公开(公告)日：2016-11-24

    申请号：US14717985

    申请日：2015-05-20

    Applicant: XILINX, INC.

    Inventor： Scott D. McLeod ,  Hsung Jai Im ,  Stanley Y. Chen

    IPC: G01R31/04 ,  H03K3/012 ,  H03K3/3568 ,  G01R31/28

    CPC classification number: G01R31/041 ,  G01R31/2884 ,  G01R31/318572 ,  H03K3/012 ,  H03K3/3568 ,  H03K19/017527 ,  H03K19/018514 ,  H04L25/0272

    Abstract: In one example, a driver circuit includes a differential transistor pair configured to be biased by a current source and including a differential input and a differential output. The driver circuit further includes a resistor pair coupled between a node pair and the differential output, a transistor pair coupled between a voltage supply and the node pair, and a bridge transistor coupled between the node pair. The driver circuit further includes a pair of three-state circuit elements having a respective pair of input ports, a respective pair of control ports, and a respective pair of output ports. The pair of output ports is respectively coupled to the node pair. The pair of control ports is coupled to a common node comprising each gate of the transistor pair and a gate of the bridge transistor.

    Abstract translation: 在一个示例中，驱动器电路包括被配置为被电流源偏置并包括差分输入和差分输出的差分晶体管对。 驱动器电路还包括耦合在节点对和差分输出之间的电阻器对，耦合在电压源和节点对之间的晶体管对以及耦合在节点对之间的桥式晶体管。 驱动器电路还包括一对三态电路元件，其具有相应的一对输入端口，相应的一对控制端口和相应的一对输出端口。 输出端口对分别耦合到节点对。 该对控制端口耦合到包括晶体管对的每个栅极和桥式晶体管的栅极的公共节点。

    High speed frequency divider
    8.
    发明授权
    High speed frequency divider 有权

    公开(公告)号：US10530375B1

    公开(公告)日：2020-01-07

    申请号：US16122761

    申请日：2018-09-05

    Applicant: Xilinx, Inc.

    Inventor： Yipeng Wang ,  Kee Hian Tan ,  Stanley Y. Chen ,  Yohan Frans

    IPC: H03B19/12 ,  H03L7/197 ,  H03L7/193

    Abstract: A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.

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