公开(公告)号：US08610515B2

公开(公告)日：2013-12-17

申请号：US13103634

申请日：2011-05-09

申请人： Xing Lan ,  Mark Kintis ,  Chad Hansen

发明人： Xing Lan ,  Mark Kintis ,  Chad Hansen

IPC分类号： H01P1/18

CPC分类号： H01P9/02

摘要： A time delay circuit including at least one spiral delay line formed on a top surface of a first substrate. In one embodiment, the delay line is defined by two concentric spiral delay line sections. Vias extend through the substrate between the delay line sections to reduce cross-talk therebetween. In another embodiment, the delay circuit includes a second substrate spaced from the first substrate, where a spiral delay line is formed on a top surface of the second substrate. A planar metal layer is provided on a backside surface of the first substrate and a conductive element extends through an opening in the metal layer and is coupled to the spiral delay lines, where the planar member provides magnetic isolation between the delay lines. In yet another embodiment, a multi-bit switched circuit can be provided on one of the substrates and be electrically connected to the delay line.

摘要翻译： 一种延迟电路，包括形成在第一基板的顶表面上的至少一个螺旋延迟线。 在一个实施例中，延迟线由两个同心的螺旋延迟线部分限定。 通孔延伸穿过延迟线部分之间的衬底，以减少它们之间的串扰。 在另一个实施例中，延迟电路包括与第一衬底间隔开的第二衬底，其中螺旋延迟线形成在第二衬底的顶表面上。 平面金属层设置在第一基板的背面上，并且导电元件延伸穿过金属层中的开口并且连接到螺旋延迟线，其中平面构件在延迟线之间提供磁隔离。 在另一个实施例中，可以在一个基板上提供多位开关电路，并且电连接到延迟线。

公开(公告)号：US20120286899A1

公开(公告)日：2012-11-15

申请号：US13103634

申请日：2011-05-09

申请人： Xing Lan ,  Mark Kintis ,  Chad Hansen

发明人： Xing Lan ,  Mark Kintis ,  Chad Hansen

IPC分类号： H01P1/18

CPC分类号： H01P9/02

摘要： A time delay circuit including at least one spiral delay line formed on a top surface of a first substrate. In one embodiment, the delay line is defined by two concentric spiral delay line sections. Vias extend through the substrate between the delay line sections to reduce cross-talk therebetween. In another embodiment, the delay circuit includes a second substrate spaced from the first substrate, where a spiral delay line is formed on a top surface of the second substrate. A planar metal layer is provided on a backside surface of the first substrate and a conductive element extends through an opening in the metal layer and is coupled to the spiral delay lines, where the planar member provides magnetic isolation between the delay lines. In yet another embodiment, a multi-bit switched circuit can be provided on one of the substrates and be electrically connected to the delay line.

摘要翻译： 一种延迟电路，包括形成在第一基板的顶表面上的至少一个螺旋延迟线。 在一个实施例中，延迟线由两个同心的螺旋延迟线部分限定。 通孔延伸穿过延迟线部分之间的衬底，以减少它们之间的串扰。 在另一个实施例中，延迟电路包括与第一衬底间隔开的第二衬底，其中螺旋延迟线形成在第二衬底的顶表面上。 平面金属层设置在第一基板的背面上，并且导电元件延伸穿过金属层中的开口并且连接到螺旋延迟线，其中平面构件在延迟线之间提供磁隔离。 在另一个实施例中，可以在一个基板上提供多位开关电路，并且电连接到延迟线。

公开(公告)号：US20080169846A1

公开(公告)日：2008-07-17

申请号：US11651989

申请日：2007-01-11

申请人： Xing Lan ,  Mark Kintis ,  Flavia S. Fong

发明人： Xing Lan ,  Mark Kintis ,  Flavia S. Fong

IPC分类号： H03B21/00 ,  G06F1/04 ,  H03K7/02

CPC分类号： H03B25/00 ,  H03K5/12

摘要： A device and method are disclosed for synthesizing a waveform having pulse segments. An exemplary generator can include units having a time delay element and pulse generator generating the pulse segments. An input divider divides an input signal into signal instances that propagate through the units and an output combiner combines pulse segments to form the waveform. The pulse generators include a sharpening circuit for sharpening a rising edge and a falling edge of the pulse segments. The sharpening circuit includes a tunable delay element coupled to a non-linear transmission line (NLTL). Another NLTL can be coupled in parallel with the tunable delay element and the first NLTL. The NLTLs include input sections coupled to anodes or cathodes of Schottky diode elements, and the respective cathodes or anodes are coupled to a signal ground.

公开(公告)号：US20070052491A1

公开(公告)日：2007-03-08

申请号：US11218968

申请日：2005-09-02

申请人： Mark Kintis ,  Flavia Fong ,  Xing Lan

发明人： Mark Kintis ,  Flavia Fong ,  Xing Lan

IPC分类号： H03H7/42

CPC分类号： H01P5/10 ,  H01F17/0006 ,  H01F2021/125 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three dimensional (3D) monolithic integrated circuit (MMIC) balun and methods of making the same are provided. A primary spiral winding is spaced apart from a secondary primary winding by a gap in a substantially aligned stacked configuration forming a balun. The gap medium can be a low dielectric constant material if employing a multi-metal process or air if employing a wafer level packaging process.

摘要翻译： 提供了三维（3D）单片集成电路（MMIC）平衡 - 不平衡变换器及其制造方法。 初级螺旋绕组与次级初级绕组间隔开一个形成一个平衡 - 不平衡变换器的基本对齐的堆叠结构的间隙。 如果使用多金属工艺或空气，如果采用晶片级封装工艺，间隙介质可以是低介电常数材料。

公开(公告)号：US20090115545A1

公开(公告)日：2009-05-07

申请号：US11934310

申请日：2007-11-02

申请人： Xing Lan ,  Mark Kintis ,  Flavia S. Fong

发明人： Xing Lan ,  Mark Kintis ,  Flavia S. Fong

IPC分类号： H03K7/08

CPC分类号： H04L25/4902 ,  H04B1/71635 ,  H04B1/7174

摘要： A modulator is provided that comprises a nonlinear transmission line (NLTL) that is bias modulated by a baseband signal. A given logic state of the baseband signal determines a delay amount of a first carrier signal through the NLTL. The modulator further comprises an impulse forming network (IFN) that includes a first NLTL that receives the first carrier signal delayed by the determined delay amount and a second NLTL that receives a second carrier signal having a fixed delay amount. The first NLTL and second NLTL within the IFN have opposite diode polarity configurations. The modulator further comprises a power combiner that converts a delta delay of the first carrier signal relative to the second carrier signal to a sharp impulse that represents the given logic state of the baseband signal.

摘要翻译： 提供了一种包括被基带信号偏置调制的非线性传输线（NLTL）的调制器。 基带信号的给定逻辑状态确定通过NLTL的第一载波信号的延迟量。 调制器还包括脉冲形成网络（IFN），其包括接收延迟了所确定的延迟量的第一载波信号的第一NLTL和接收具有固定延迟量的第二载波信号的第二NLTL。 IFN中的第一个NLTL和第二个NLTL具有相反的二极管极性配置。 调制器还包括功率组合器，其将第一载波信号相对于第二载波信号的增量延迟转换为表示基带信号的给定逻辑状态的尖锐脉冲。

公开(公告)号：US07462956B2

公开(公告)日：2008-12-09

申请号：US11651989

申请日：2007-01-11

申请人： Xing Lan ,  Mark Kintis ,  Flavia S. Fong

发明人： Xing Lan ,  Mark Kintis ,  Flavia S. Fong

IPC分类号： H03K3/64 ,  H03K5/06 ,  H03K5/12

CPC分类号： H03B25/00 ,  H03K5/12

摘要： A device and method are disclosed for synthesizing a waveform having pulse segments. An exemplary generator can include units having a time delay element and pulse generator generating the pulse segments. An input divider divides an input signal into signal instances that propagate through the units and an output combiner combines pulse segments to form the waveform. The pulse generators include a sharpening circuit for sharpening a rising edge and a falling edge of the pulse segments. The sharpening circuit includes a tunable delay element coupled to a non-linear transmission line (NLTL). Another NLTL can be coupled in parallel with the tunable delay element and the first NLTL. The NLTLs include input sections coupled to anodes or cathodes of Schottky diode elements, and the respective cathodes or anodes are coupled to a signal ground.

摘要翻译： 公开了一种用于合成具有脉冲段的波形的装置和方法。 示例性发生器可以包括具有时间延迟元件的单元和产生脉冲段的脉冲发生器。 输入分频器将输入信号分成通过单元传播的信号实例，输出组合器组合脉冲段以形成波形。 脉冲发生器包括用于锐化脉冲段的上升沿和下降沿的锐化电路。 锐化电路包括耦合到非线性传输线（NLTL）的可调谐延迟元件。 另一个NLTL可以与可调谐延迟元件和第一个NLTL并联耦合。 NLTL包括耦合到肖特基二极管元件的阳极或阴极的输入部分，并且相应的阴极或阳极耦合到信号地。

公开(公告)号：US07276981B2

公开(公告)日：2007-10-02

申请号：US11236033

申请日：2005-09-27

申请人： Mark Kintis ,  Flavia S. Fong ,  Thomas T. Y. Wong ,  Xing Lan

发明人： Mark Kintis ,  Flavia S. Fong ,  Thomas T. Y. Wong ,  Xing Lan

IPC分类号： H03B5/00

CPC分类号： H03B5/1841

摘要： A three dimensional (3D) microwave monolithic integrated circuit (MMIC) multi-push voltage controlled oscillator (VCO) and methods of making the same is provided. The 3D MMIC multi-push oscillator includes a plurality of matching frequency oscillators coupled to a phasing ring in substantially equidistantly spaced apart locations. A combined VCO output signal is provided at a central output connection point of the phasing ring. The central output connection point resides on a first plane. An output conductor transition has a first end coupled to the central output connection point and a second end provided as an output to the quad-push VCO. The output conductor transition extends transverse to the first plane and terminates at a second plane separated from the first plane. The multi-push oscillator can be a push-push, quad-push or N-push type VCO based on a particular implementation.

公开(公告)号：US07733194B2

公开(公告)日：2010-06-08

申请号：US11934310

申请日：2007-11-02

申请人： Xing Lan ,  Mark Kintis ,  Flavia S. Fong

发明人： Xing Lan ,  Mark Kintis ,  Flavia S. Fong

IPC分类号： H04B3/04

CPC分类号： H04L25/4902 ,  H04B1/71635 ,  H04B1/7174

摘要： A modulator is provided that comprises a nonlinear transmission line (NLTL) that is bias modulated by a baseband signal. A given logic state of the baseband signal determines a delay amount of a first carrier signal through the NLTL. The modulator further comprises an impulse forming network (IFN) that includes a first NLTL that receives the first carrier signal delayed by the determined delay amount and a second NLTL that receives a second carrier signal having a fixed delay amount. The first NLTL and second NLTL within the IFN have opposite diode polarity configurations. The modulator further comprises a power combiner that converts a delta delay of the first carrier signal relative to the second carrier signal to a sharp impulse that represents the given logic state of the baseband signal.

摘要翻译： 提供了一种包括被基带信号偏置调制的非线性传输线（NLTL）的调制器。 基带信号的给定逻辑状态确定通过NLTL的第一载波信号的延迟量。 调制器还包括脉冲形成网络（IFN），其包括接收延迟了所确定的延迟量的第一载波信号的第一NLTL和接收具有固定延迟量的第二载波信号的第二NLTL。 IFN中的第一个NLTL和第二个NLTL具有相反的二极管极性配置。 调制器还包括功率组合器，其将第一载波信号相对于第二载波信号的增量延迟转换为表示基带信号的给定逻辑状态的尖锐脉冲。

公开(公告)号：US07570137B2

公开(公告)日：2009-08-04

申请号：US11288049

申请日：2005-11-14

申请人： Mark Kintis ,  Flavia S. Fong ,  Thomas T. Y. Wong ,  Xing Lan

发明人： Mark Kintis ,  Flavia S. Fong ,  Thomas T. Y. Wong ,  Xing Lan

IPC分类号： H01P7/06

CPC分类号： H01P7/065

摘要： A ferroelectric loaded waveguide resonator capable of operation at microwave, millimeter-wave and higher frequencies and suitable for integration into a three-dimensional monolithic microwave integrated circuit (3D MMIC) is disclosed. The resonator includes a resonator cavity, which, in one form of the invention, is formed by two parallel metal layers and a metallized wall structure extending between the metal layers. The cavity is filled with dielectric material and includes a layer of ferroelectric material, which is used to control the resonant frequency by varying a voltage bias applied to the ferroelectric layer. The cavity includes a slot in one of the metal layers and a coupling strip formed adjacent to the slot to provide electromagnetic coupling to other components, such as a voltage controlled oscillator (VCO). The invention can also be applied to other multi-metal semiconductor or wafer level packaging technologies.

摘要翻译： 公开了一种能够在微波，毫米波和更高频率下操作并且适合于集成到三维单片微波集成电路（3D MMIC）中的铁电负载波导谐振器。 谐振器包括谐振器腔，其在本发明的一种形式中由两个平行的金属层和在金属层之间延伸的金属化壁结构形成。 空腔填充有电介质材料，并且包括铁电材料层，其用于通过改变施加到铁电层的电压偏压来控制谐振频率。 空腔包括在金属层中的一个中的槽和与槽相邻形成的耦合条，以提供与其它部件（例如压控振荡器（VCO））的电磁耦合。 本发明也可应用于其他多金属半导体或晶圆级封装技术。

公开(公告)号：US07570129B2

公开(公告)日：2009-08-04

申请号：US11218968

申请日：2005-09-02

申请人： Mark Kintis ,  Flavia S. Fong ,  Xing Lan

发明人： Mark Kintis ,  Flavia S. Fong ,  Xing Lan

IPC分类号： H01F5/00

CPC分类号： H01P5/10 ,  H01F17/0006 ,  H01F2021/125 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three dimensional (3D) monolithic integrated circuit (MMIC) balun and methods of making the same are provided. A primary spiral winding is spaced apart from a secondary primary winding by a gap in a substantially aligned stacked configuration forming a balun. The gap medium can be a low dielectric constant material if employing a multi-metal process or air if employing a wafer level packaging process.

摘要翻译： 提供了三维（3D）单片集成电路（MMIC）平衡 - 不平衡变换器及其制造方法。 初级螺旋绕组与次级初级绕组间隔开一个形成一个平衡 - 不平衡变换器的基本对齐的堆叠结构的间隙。 如果使用多金属工艺或空气，如果采用晶片级封装工艺，间隙介质可以是低介电常数材料。