公开(公告)号：US08098525B2

公开(公告)日：2012-01-17

申请号：US12232437

申请日：2008-09-17

申请人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

发明人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C7/12 ,  G11C7/18 ,  G11C16/26

摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.

摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 根据每个地址的预定义表格选择预充电的全局位线。 根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

公开(公告)号：US20120063238A1

公开(公告)日：2012-03-15

申请号：US13301826

申请日：2011-11-22

申请人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

发明人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

IPC分类号： G11C16/06

CPC分类号： G11C16/0475 ,  G11C7/12 ,  G11C7/18 ,  G11C16/26

摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.

摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 根据每个地址的预定义表格选择预充电的全局位线。 根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

公开(公告)号：US08593881B2

公开(公告)日：2013-11-26

申请号：US13301826

申请日：2011-11-22

申请人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

发明人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C7/12 ,  G11C7/18 ,  G11C16/26

摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines are selected according to a pre-defined table per each address. The selection of the global bitlines is done according to whether these global bitlines will interfere with the pipe during the next read cycle.

摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 根据每个地址的预定义表格选择预充电的全局位线。 根据在下一个读取周期期间这些全局位线是否会干扰管道，完成全局位线的选择。

公开(公告)号：US20090073774A1

公开(公告)日：2009-03-19

申请号：US12232437

申请日：2008-09-17

申请人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

发明人： Yaal Horesh ,  Oleg Dadashev ,  Yoram Betser ,  Avri Harush

IPC分类号： G11C16/06 ,  G11C7/00

CPC分类号： G11C16/0475 ,  G11C7/12 ,  G11C7/18 ,  G11C16/26

摘要： The pipe effect can significantly degrade flash performance. A method to significantly reduce pipe current and (or neighbor current using a pre-charge sequence) is disclosed. A dedicated read order keeps the sensing node facing the section of the pipe which was pre-charged. The technique involves pre-charging several global bitlines (such as metal bitlines, or MBLs) and local bitlines (such as diffusion bitlines, or DBLs). The pre-charged global bitlines may be selected according to a pre-defined table per each address. The selection of the global bitlines may be done according to whether these global bitlines will interfere with the pipe during the next read cycle.

摘要翻译： 管道效应可以显着降低闪存性能。 公开了一种显着减少管电流和（或使用预充电顺序的相邻电流）的方法。 专用的读取顺序使感测节点面向预先充电的管道的部分。 该技术涉及预充电几个全局位线（例如金属位线或MBL）和本地位线（例如扩散位线或DBL）。 可以根据每个地址的预定义表来选择预充电的全局位线。 可以根据在下一个读取周期期间这些全局位线是否会干扰管道来完成全局位线的选择。

公开(公告)号：US07864588B2

公开(公告)日：2011-01-04

申请号：US12232418

申请日：2008-09-17

申请人： Yoram Betser ,  Yair Sofer ,  Oren Shlomo ,  Avri Harush

发明人： Yoram Betser ,  Yair Sofer ,  Oren Shlomo ,  Avri Harush

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/28 ,  G11C16/3427

摘要： A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.

摘要翻译： 一种通过使用第一漏极电压来读取阵列单元并使用第二较低漏极电压来读取参考单元的方法来减小NVM单元中的读取干扰。 阵列和参考单元的全局位线（GBL）上的漏极电压可能彼此基本相同，以保持主路径电容匹配，而参考单元的局部位线（LBL）上的漏极电压可能低于漏极 本地位线上的电压（LBL）用于阵列单元以减少第二位效应。 可以使用夹紧装置或降压装置来降低其排出口处的参考单元的漏极电压。

公开(公告)号：US20090073760A1

公开(公告)日：2009-03-19

申请号：US12232418

申请日：2008-09-17

申请人： Yoram Betser ,  Yair Sofer ,  Oren Shlomo ,  Avri Harush

发明人： Yoram Betser ,  Yair Sofer ,  Oren Shlomo ,  Avri Harush

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0475 ,  G11C16/28 ,  G11C16/3427

摘要： A method of reducing read disturb in NVM cells by using a first drain voltage to read the array cells and using a second, lower drain voltage, to read the reference cells. Drain voltages on global bitlines (GBLs) for both the array and the reference cells may be substantially the same as one another to maintain main path capacitance matching, while drain voltages on local bitlines (LBLs) for the reference cells may be lower than the drain voltage on local bitlines (LBLs) for the array cells to reduce second bit effect. Reducing the drain voltage of the reference cell at its drain port may be performed using a clamping device or a voltage drop device.

摘要翻译： 一种通过使用第一漏极电压来读取阵列单元并使用第二较低漏极电压来读取参考单元的方法来减小NVM单元中的读取干扰。 阵列和参考单元的全局位线（GBL）上的漏极电压可能彼此基本相同，以保持主路径电容匹配，而参考单元的局部位线（LBL）上的漏极电压可能低于漏极 本地位线上的电压（LBL）用于阵列单元以减少第二位效应。 可以使用夹紧装置或降压装置来降低其排出口处的参考单元的漏极电压。

公开(公告)号：US06842383B2

公开(公告)日：2005-01-11

申请号：US10354050

申请日：2003-01-30

申请人： Joseph S. Shor ,  Avri Harush ,  Shai Eisen

发明人： Joseph S. Shor ,  Avri Harush ,  Shai Eisen

IPC分类号： G11C8/08 ,  G11C7/00

CPC分类号： G11C8/08

摘要： According to some embodiments of the present invention, a non-volatile memory cell may be operated using a charge pump circuit. The charge pump circuit may be adapted to output a first and second voltage level, and the charge pump circuit may be connected to a first circuit segment, including a select transistor associated with the memory cell, through a switch. When the charge pump circuit is outputting power at the first voltage level, the switch may be conducting and the select transistor line may be charged. When the charge pump circuit is outputting power at the second voltage level, the switch may be opened and a second circuit segment, including a bit line associated with the memory cell, may be charged.

摘要翻译： 根据本发明的一些实施例，可以使用电荷泵电路来操作非易失性存储单元。 电荷泵电路可以适于输出第一和第二电压电平，并且电荷泵电路可以通过开关连接到包括与存储器单元相关联的选择晶体管的第一电路段。 当电荷泵电路以第一电压电平输出功率时，开关可以导通，并且选择晶体管线可以被充电。 当电荷泵电路以第二电压电平输出功率时，可以打开开关，并且可以对包括与存储单元相关联的位线的第二电路段进行充电。