公开(公告)号：US5510629A

公开(公告)日：1996-04-23

申请号：US250068

申请日：1994-05-27

申请人： Yakov Karpovich ,  Ali A. Iranmanesh

发明人： Yakov Karpovich ,  Ali A. Iranmanesh

IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L29/04 ,  H01L31/036

CPC分类号： H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002

摘要： A method and structure for an improved antifuse in an integrated circuit having a sacrificial layer under a programming layer which forces a conductive link upon programming to be formed away from corner regions of the via structures. The method includes the unique step of forming an improved aperture or via with sides through an inter dielectric layer where the antifuse is to be located. The improved aperture or via exposes a portion of a metal interconnection line through a portion of sacrificial layer located away from the inter dielectric layer sides. Such improved method of forming the antifuse also provides a superior antifuse structure.

摘要翻译： 在集成电路中具有改进的反熔丝的方法和结构，其具有在编程层下方的牺牲层，其在编程时迫​​使导电连接件远离通孔结构的拐角区域。 该方法包括通过反熔丝所在的介质层形成改进的孔或通孔的独特步骤。 改进的孔径或通孔暴露金属互连线的一部分穿过远离介电层侧面的牺牲层的一部分。 这种改进的形成反熔丝的方法也提供了优异的反熔丝结构。

公开(公告)号：US5786240A

公开(公告)日：1998-07-28

申请号：US672185

申请日：1996-06-27

申请人： Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

发明人： Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/055

摘要： An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.

公开(公告)号：US5726484A

公开(公告)日：1998-03-10

申请号：US611897

申请日：1996-03-06

申请人： Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

发明人： Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

IPC分类号： H01L23/525 ,  H01L29/04 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

摘要翻译： 提供了包括第一和第二导电层以及位于第一和第二导电层之间的反熔丝层的防潮装置。 反熔丝层包括位于两个非晶硅层之间的至少一个氧化物层。 还提供了互连结构和可编程逻辑器件，其包括反熔丝。

公开(公告)号：US6057589A

公开(公告)日：2000-05-02

申请号：US61817

申请日：1998-04-16

申请人： Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

发明人： Kevin T. Look ,  Yakov Karpovich ,  Michael J. Hart

IPC分类号： H01L23/525 ,  H01L29/00 ,  H01L21/70

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.

摘要翻译： 过蚀刻（OE）反熔丝包括下电极，通过过蚀刻通孔与下电极接触的反熔丝层，以及形成在反熔丝层上的第二导电层。 该过蚀刻通孔在下电极中形成沟槽，其中在一个实施例中，沟槽的深度接近反熔丝层的厚度。 沟槽缩小了设备上反熔文件的编程电压分布，而不考虑拓扑结构。 由于有源电路可以放置在OE反熔丝之下，因此与传统的器件相比，本发明显着地减小了芯片的尺寸。

公开(公告)号：US5970372A

公开(公告)日：1999-10-19

申请号：US1022

申请日：1997-12-30

申请人： Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

发明人： Michael J. Hart ,  Kevin T. Look ,  Yakov Karpovich

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic devices are also provided which include the antifuses.

摘要翻译： 提供了包括第一和第二导电层以及位于第一和第二导电层之间的反熔丝层的防潮装置。 反熔丝层包括位于两个非晶硅层之间的至少一个氧化物层。 还提供了互连结构和可编程逻辑器件，其包括反熔丝。

公开(公告)号：US6033938A

公开(公告)日：2000-03-07

申请号：US751193

申请日：1996-11-15

申请人： Martin L. Voogel ,  Yakov Karpovich ,  Michael J. Hart

发明人： Martin L. Voogel ,  Yakov Karpovich ,  Michael J. Hart

IPC分类号： H01L23/525 ,  H01L21/82

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： Treatment of the positive electrode interface of an antifuse provides significantly improved on-state reliability. Treatments include, but are not limited to, a plasma etch using carbon tetrafluoride (CF.sub.4), a sputter clean using Argon, and wet chemical treatments using dimethyl formamide (and water) or a resist developer.

摘要翻译： 反熔丝的正极接口的处理提供了显着改善的导通状态可靠性。 处理包括但不限于使用四氟化碳（CF4）的等离子体蚀刻，使用氩气的溅射清洁以及使用二甲基甲酰胺（和水）或抗蚀剂显影剂的湿化学处理。

公开(公告)号：US5523612A

公开(公告)日：1996-06-04

申请号：US154842

申请日：1993-11-19

申请人： Yakov Karpovich

发明人： Yakov Karpovich

IPC分类号： H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A method of forming an antifuse in an integrated circuit having an insulating layer on a semiconductor substrate is provided. The method comprises forming a first metal interconnection layer on the insulating layer; forming a first barrier metal layer on the first metal interconnection layer; forming an amorphous silicon layer on the first barrier metal layer; forming another barrier metal layer atop the amorphous silicon layer; and forming a second metal interconnection layer on the second barrier metal layer. In at least one of the barrier metal forming steps, the barrier metal is formed by sputtering a barrier metal target which includes a semiconductor dopant, such as dopant.

摘要翻译： 提供了在半导体衬底上具有绝缘层的集成电路中形成反熔丝的方法。 该方法包括在绝缘层上形成第一金属互连层; 在所述第一金属互连层上形成第一阻挡金属层; 在所述第一阻挡金属层上形成非晶硅层; 在所述非晶硅层的顶部形成另一阻挡金属层; 以及在所述第二阻挡金属层上形成第二金属互连层。 在至少一个阻挡金属形成步骤中，通过溅射包括诸如掺杂剂的半导体掺杂剂的阻挡金属靶形成阻挡金属。