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1.发明授权公开(公告)号：US07961512B2
公开(公告)日：2011-06-14
申请号：US12051462
申请日：2008-03-19
申请人： Yan Li , Anne Pao-Ling Koh
发明人： Yan Li , Anne Pao-Ling Koh
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G06F12/0855 , G06F2212/2022 , G11C7/1039 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C2207/2245 , G11C2211/5623 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed. The memory subsequently can perform the second operation during the first operation when a sufficient number of latches become available; and if, in response to determining whether there are a sufficient number of the corresponding set of data latches to perform the second operation it is determined that there are a sufficient number, performing the second operation during the first operation.
摘要翻译： 非易失性存储器可以使用存储在相应的数据锁存器组中的第一组数据来执行一个或多个寻址页面的指定组上的第一操作（例如写入），并且还接收对 还使用具有第二组数据的这些相应的数据锁存器中的一些的第二操作（例如读取）。 在第一操作期间，当对应的每组的至少一个锁存器变得可用于第二操作时，存储器是否存在足够数量的对应的一组数据锁存器以在第一操作期间执行第二操作; 如果没有，则第二操作被延迟。 当足够数量的锁存器变得可用时，存储器随后可以在第一操作期间执行第二操作; 并且如果响应于确定是否存在足够数量的对应的数据锁存器组来执行第二操作，则确定存在足够的数量，在第一操作期间执行第二操作。
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2.发明申请公开(公告)号：US20090237998A1
公开(公告)日：2009-09-24
申请号：US12051462
申请日：2008-03-19
申请人： Yan Li , Anne Pao-Ling Koh
发明人： Yan Li , Anne Pao-Ling Koh
CPC分类号： G11C16/10 , G06F12/0855 , G06F2212/2022 , G11C7/1039 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C2207/2245 , G11C2211/5623 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed. The memory subsequently can perform the second operation during the first operation when a sufficient number of latches become available; and if, in response to determining whether there are a sufficient number of the corresponding set of data latches to perform the second operation it is determined that there are a sufficient number, performing the second operation during the first operation.
摘要翻译： 非易失性存储器可以使用存储在相应的数据锁存器组中的第一组数据来执行一个或多个寻址页面的指定组上的第一操作（例如写入），并且还接收对 还使用具有第二组数据的这些相应的数据锁存器中的一些的第二操作（例如读取）。 在第一操作期间，当对应的每组的至少一个锁存器变得可用于第二操作时，存储器是否存在足够数量的对应的一组数据锁存器以在第一操作期间执行第二操作; 如果没有，则第二操作被延迟。 当足够数量的锁存器变得可用时，存储器随后可以在第一操作期间执行第二操作; 并且如果响应于确定是否存在足够数量的对应的数据锁存器组来执行第二操作，则确定存在足够的数量，在第一操作期间执行第二操作。
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3.发明授权Integrated circuit memory device with bit line pre-charging based upon partial address decoding 有权具有基于部分地址解码的位线预充电的集成电路存储器件公开(公告)号：US07009886B1
公开(公告)日：2006-03-07
申请号：US10893809
申请日：2004-07-19
IPC分类号： G11C16/06
CPC分类号： G11C7/12
摘要： An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same row are connected by a common row line, and cells arranged in the same column are connected by a common column line. Each cell in the array is addressed by an address signal which has a plurality of bits. A sense amplifier circuit is connectable to one or more of the plurality of column lines of the array. An address input terminal receives in series the plurality of bits of the address signal. Each of the column lines is connectable to a pre-charge voltage, in response to a read command. A decoder circuit receives the address signal and decodes the address signal as each of the plurality of bits is received and disconnects certain of the column lines to the pre-charge voltage in response to the decoding, and activates the sense amplifier circuit after all of the plurality of bits of the address signal are received.
摘要翻译： 集成电路存储器件具有排列成多个行和列以及多条行线和多条列线的存储单元阵列。 布置在同一行中的单元通过公共行线连接，并且排列在同一列中的单元通过公共列线连接。 阵列中的每个单元由具有多个位的地址信号寻址。 读出放大器电路可连接到阵列的多个列线中的一个或多个。 地址输入端串联地址信号的多个位。 响应读取命令，每列列线可连接到预充电电压。 解码器电路接收地址信号并且在接收到多个比特中的每一个时对地址信号进行解码，并且响应于解码将某些列线断开到预充电电压，并且在全部 接收地址信号的多个位。
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公开(公告)号：US07027348B2
公开(公告)日：2006-04-11
申请号：US10921754
申请日：2004-08-17
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C7/1027 , G11C7/103
摘要： An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit. The control circuit receives a read command, and a clock signal, and in response to the read command activates a first plurality (j) of the plurality (k) of sense amplifiers (j
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