公开(公告)号：US20130155769A1

公开(公告)日：2013-06-20

申请号：US13329103

申请日：2011-12-16

申请人： Yan Li ,  Cynthia Hsu ,  Ken Oowada

发明人： Yan Li ,  Cynthia Hsu ,  Ken Oowada

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3468

摘要： A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The memory cells operate within a common threshold voltage range or window, which is partitioned into multiple bands to denote a series of increasingly programmed states. The series is divided into two halves, a lower set and a higher set. The memory cells are programmed in a first, coarse programming pass such that the memory cells of the page with target states from the higher set are programmed to a staging area near midway in the threshold window. In particular, they are programmed closer to their targeted destinations than previous schemes, without incurring much performance penalty. Subsequent passes will then complete the programming more quickly. Yuping effect is reduced since the threshold voltage change in subsequent passes are reduced.

摘要翻译： 具有多遍编程方案的非易失性存储器使得能够以降低的浮栅到浮栅扰动（Yuping效应）来编程一页多层存储单元。 存储器单元在公共阈值电压范围或窗口内工作，其被划分为多个频带以表示一系列日益编程的状态。 该系列分为两部分，一组较低，一组较高。 存储器单元被编程在第一粗略编程遍历中，使得具有来自较高集合的目标状态的页面的存储器单元被编程到阈值窗口中途附近的分段区域。 特别地，它们被编程为比先前的方案更接近目标目的地，而不会导致太多的性能损失。 随后的通行证将更快地完成编程。 Yuping效应降低，因为后续通过中的阈值电压变化减小。

公开(公告)号：US08811091B2

公开(公告)日：2014-08-19

申请号：US13329103

申请日：2011-12-16

申请人： Yan Li ,  Cynthia Hsu ,  Ken Oowada

发明人： Yan Li ,  Cynthia Hsu ,  Ken Oowada

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3468

摘要： A nonvolatile memory with a multi-pass programming scheme enables a page of multi-level memory cells to be programmed with reduced floating-gate to floating-gate perturbations (Yuping effect). The memory cells operate within a common threshold voltage range or window, which is partitioned into multiple bands to denote a series of increasingly programmed states. The series is divided into two halves, a lower set and a higher set. The memory cells are programmed in a first, coarse programming pass such that the memory cells of the page with target states from the higher set are programmed to a staging area near midway in the threshold window. In particular, they are programmed closer to their targeted destinations than previous schemes, without incurring much performance penalty. Subsequent passes will then complete the programming more quickly. Yuping effect is reduced since the threshold voltage change in subsequent passes are reduced.

摘要翻译： 具有多遍编程方案的非易失性存储器使得能够以降低的浮栅到浮栅扰动（Yuping效应）来编程一页多层存储单元。 存储器单元在公共阈值电压范围或窗口内工作，其被划分为多个频带以表示一系列日益编程的状态。 该系列分为两部分，一组较低，一组较高。 存储器单元被编程在第一粗略编程遍历中，使得具有来自较高集合的目标状态的页面的存储器单元被编程到阈值窗口中途附近的分段区域。 特别地，它们被编程为比先前的方案更接近目标目的地，而不会导致太多的性能损失。 随后的通行证将更快地完成编程。 Yuping效应降低，因为后续通过中的阈值电压变化减小。

公开(公告)号：US20120243323A1

公开(公告)日：2012-09-27

申请号：US13071170

申请日：2011-03-24

申请人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

发明人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3468

摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.

摘要翻译： 非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。 存储器状态由一组增加的分界阈值（V1，...，VN）划分。 最初在编程过程中，相对于测试参考阈值验证存储器单元。 该测试参考阈值具有超过设定中的指定分界阈值Vi的值偏移预定余量。 可以确定当经过Vi编程时每个存储单元的过冲大于或小于余量。 因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

公开(公告)号：US08472257B2

公开(公告)日：2013-06-25

申请号：US13071170

申请日：2011-03-24

申请人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

发明人： Yingda Dong ,  Ken Oowada ,  Cynthia Hsu

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3468

摘要： A group of memory cells of a nonvolatile memory is programmed in parallel in a programming pass with a minimum of verify steps from an erased state to respective target states by a staircase waveform. The memory states are demarcated by a set of increasing demarcation threshold values (V1, . . . , VN). Initially in the programming pass, the memory cells are verified relative to a test reference threshold value. This test reference threshold has a value offset past a designate demarcation threshold value Vi among the set by a predetermined margin. The overshoot of each memory cell when programmed past Vi, to be more or less than the margin can be determined. Accordingly, memory cells found to have an overshoot more than the margin are counteracted by having their programming rate slowed down in a subsequent portion of the programming pass so as to maintain a tighter threshold distribution.

摘要翻译： 非易失性存储器的一组存储器单元在编程通道中并行编程，其中通过阶梯波形具有从擦除状态到各个目标状态的最小验证步骤。 存储器状态由一组增加的分界阈值（V1，...，VN）划分。 最初在编程过程中，相对于测试参考阈值验证存储器单元。 该测试参考阈值具有超过设定中的指定分界阈值Vi的值偏移预定余量。 可以确定当经过Vi编程时每个存储单元的过冲大于或小于余量。 因此，发现超过裕度的超调的存储器单元的编程速率在编程通过的后续部分中变慢，以便保持更严格的阈值分布而被抵消。

公开(公告)号：US08743615B2

公开(公告)日：2014-06-03

申请号：US13214765

申请日：2011-08-22

申请人： Dana Lee ,  Ken Oowada

发明人： Dana Lee ,  Ken Oowada

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3427 ,  G11C11/5642

摘要： Read compensation for partially programmed blocks of non-volatile storage is provided. In partially programmed blocks, the threshold voltage distributions may be shifted down relative to their final positions. Upon receiving a request to read a page that is stored in a block, a determination may be made whether the block is partially programmed. If so, then a suitable compensation may be made when reading the requested page. This compensation may compensate for the non-volatile storage elements (or pages) in the block that have not yet been programmed. The amount of compensation may be based on the amount of interference that would be caused to the requested page by later programming of the other pages. The compensation may compensate for shifts in threshold voltage distributions of the requested page that would occur from later programming of other pages.

摘要翻译： 提供了部分编程的非易失性存储块的读取补偿。 在部分编程的块中，阈值电压分布可以相对于其最终位置向下移动。 在接收到读取存储在块中的页面的请求时，可以确定块是否被部分编程。 如果是这样，那么在阅读请求的页面时可以做出适当的补偿。 该补偿可以补偿块中尚未编程的非易失性存储元件（或页）。 赔偿金额可以基于通过稍后对其他页面进行编程而对所请求的页面造成的干扰量。 该补偿可以补偿所请求的页面的阈值电压分布的变化，其将从其他页面的后续编程发生。

公开(公告)号：US20140003147A1

公开(公告)日：2014-01-02

申请号：US13537551

申请日：2012-06-29

申请人： Deepanshu Dutta ,  Ken Oowada ,  Koichi Nishimura ,  Yingda Dong

发明人： Deepanshu Dutta ,  Ken Oowada ,  Koichi Nishimura ,  Yingda Dong

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/16 ,  G11C16/344

摘要： In connection with an erase operation of a block of non-volatile storage elements, a determination is made as to whether the block is partially but not fully programmed. A degree of partial programming can be determined by a pre-erase read operation which determines a highest programmed word line, or which determines whether there is a programmed storage element in a subset of word lines above a small subset of source side word lines. Since a partially programmed block will pass an erase-verify test more easily than a fully programmed block, a measure is taken to ensure that the block is sufficiently deeply erased. In one approach, an erase-verify test is made stricter by adjusting a sensing parameter when the block is partially programmed. In another approach, the block can be programmed before being erased. Or, an extra erase pulse which is not followed by an erase-verify test can be applied.

摘要翻译： 关于非易失性存储元件块的擦除操作，确定块是部分地还是不完全编程的。 部分编程的程度可以通过确定最高编程字线的预擦除读取操作来确定，或者确定在源侧字线的小子集之上的字线子集中是否存在编程存储元件。 由于部分编程的块将比完全编程的块更容易通过擦除验证测试，因此采取措施确保块被深度擦除。 在一种方法中，通过在块被部分编程时调整感测参数，擦除验证测试变得更严格。 在另一种方法中，块可以被擦除之前被编程。 或者，可以应用不跟随擦除验证测试的额外擦除脉冲。

公开(公告)号：US08130551B2

公开(公告)日：2012-03-06

申请号：US12751265

申请日：2010-03-31

申请人： Ken Oowada ,  Yingda Dong ,  Deepanshu Dutta

发明人： Ken Oowada ,  Yingda Dong ,  Deepanshu Dutta

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C16/14 ,  G11C16/3436

摘要： An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached, at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes. The second phase applies one or more extra erase pulses which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write-erase endurance, while still achieving the desired deep erase.

摘要翻译： 用于非易失性存储器的擦除操作包括第一和第二相。 第一阶段将一系列电压脉冲施加到衬底，其中每个擦除脉冲之后是验证操作。 验证操作使用从最终期望的阈值电压电平偏移的验证电平。 擦除脉冲以幅度升高直到达到最大电平，此时施加最大电平的附加擦除脉冲。 当验证操作通过时，第一阶段结束。 第二阶段施加一个或多个额外的擦除脉冲，其幅度高于第一阶段中的最后一个擦除脉冲，并且其后跟无验证操作。 这避免了在深的负阈值电压电平下执行验证操作的需要，这可能导致电荷捕获，从而减少写擦除耐久性，同时仍然实现期望的深度擦除。

公开(公告)号：US20110255345A1

公开(公告)日：2011-10-20

申请号：US12762342

申请日：2010-04-18

申请人： Yingda Dong ,  Shih-Chung Lee ,  Ken Oowada

发明人： Yingda Dong ,  Shih-Chung Lee ,  Ken Oowada

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，使用随时间增加的编程信号将第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，使用已经响应于第一触发而被大幅度降低的编程信号，将第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起编程，响应于第二触发而使编程信号升高。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US07460404B1

公开(公告)日：2008-12-02

申请号：US11745082

申请日：2007-05-07

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Shih-Chung Lee ,  Gerrit Jan Hemink ,  Ken Oowada

IPC分类号： G11C16/00

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.

摘要翻译： 在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。 使用包括隔离字线的自增强模式。 禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。 此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。 以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。 在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

公开(公告)号：US07428165B2

公开(公告)日：2008-09-23

申请号：US11394460

申请日：2006-03-30

申请人： Ken Oowada

发明人： Ken Oowada

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/3427 ,  H01L27/115

摘要： In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g. inverse function) of distance of the selected word line from the drain side select gate to reduce program disturb due to high vertical and lateral electric fields at or near the isolation transistor when programming word lines closer to the drain side select gate. The selected and isolation word lines are preferably separated by two or more word lines to which intermediate voltage(s) are applied.

摘要翻译： 在用于闪存器件（例如，NAND闪存器件）的改进的EASB编程方案中，分离所选字线（施加了编程电压）和隔离字线（施加隔离电压）的字线数量 ）作为所选字线距漏极侧选择栅极的距离的函数（例如反函数）进行调整，以在编程更接近漏极的字线时减少由隔离晶体管或其附近的高垂直和横向电场引起的编程干扰 侧选门。 所选择的隔离字线优选地被施加中间电压的两条或多条字线分开。