利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.017 秒)

    DUAL STAGE DRAM MEMORY EQUALIZATION
    2.
    发明申请
    DUAL STAGE DRAM MEMORY EQUALIZATION 有权
    双级DRAM内存均衡

    公开(公告)号：US20060044901A1

    公开(公告)日：2006-03-02

    申请号：US10926357

    申请日：2004-08-26

    申请人： Yangsung Joo ,  David Pinney ,  Jason Brown

    发明人： Yangsung Joo ,  David Pinney ,  Jason Brown

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

    摘要： A memory device equilibrates voltages in a bit line pair to a reduced voltage level. The reduced equilibrate voltage level can be achieved by separating the conventional equilibrate process so that the positive portion and the negative portion of the sense amplifier are equilibrated at different times. Bit line equilibration can be associated with either the equilibrate step associated with the positive portion of the sense amplifier or the equilibrate step associated with the negative portion of the sense amplifier.

    摘要翻译： 存储器件将位线对中的电压平衡到降低的电压电平。 降低的平衡电压电平可以通过分离常规的平衡过程来实现，使得感测放大器的正部分和负部分在不同时间平衡。 位线平衡可以与与感测放大器的正部分相关联的平衡步骤或与读出放大器的负部分相关联的平衡步骤相关联。

    Low voltage sense amplifier and sensing method
    4.
    发明申请
    Low voltage sense amplifier and sensing method 有权
    低电压检测放大器和感测方式

    公开(公告)号：US20070268764A1

    公开(公告)日：2007-11-22

    申请号：US11436863

    申请日：2006-05-17

    申请人： Tae Kim ,  Charles L. Ingalls ,  David Pinney ,  Howard Kirsch

    发明人： Tae Kim ,  Charles L. Ingalls ,  David Pinney ,  Howard Kirsch

    IPC分类号： G11C7/00

    CPC分类号： G11C7/08 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/2227

    摘要： Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the digit line, the digit line is coupled to a sense node and driving voltages provided to the sense amplifier. The data state is latched in response to the driving voltages. In coupling the digit line to a sense amplifier, the digit line is coupled to the sense amplifier for a first time period and decoupled from the sense amplifier for a second time period. The digit line is coupled to the sense amplifier at a controlled rate following the second time period.

    摘要翻译： 感测耦合到数字线并且将数字线耦合到读出放大器的数据状态的系统和方法。 在感测耦合到数字线的数据状态时，数字线耦合到感测节点并且提供给读出放大器的驱动电压。 响应于驱动电压而锁存数据状态。 在将数字线耦合到读出放大器时，数字线在第一时间段耦合到读出放大器，并在第二时间段内从读出放大器去耦。 数字线以跟随第二时间段的受控速率耦合到读出放大器。

    CMOS output pull-up driver
    5.
    发明授权
    CMOS output pull-up driver 失效
    CMOS输出上拉驱动

    公开(公告)号：US5150186A

    公开(公告)日：1992-09-22

    申请号：US665558

    申请日：1991-03-06

    申请人： David Pinney ,  Gary Johnson ,  Greg Roberts ,  Steve Casper

    发明人： David Pinney ,  Gary Johnson ,  Greg Roberts ,  Steve Casper

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00361

    摘要： A CMOS integrated circuit output terminal driver subcircuit (60) provides quick response at an output terminal (56) of an integrated circuit (50) while preventing reverse current leakage when an external high voltage, which exceeds the positive internal circuit source voltage of the integrated circuit, is imposed on the output terminal (56). The output driver subcircuit (60) additionally provides an output voltage at the output terminal that is only nominally below the internal circuit source voltage. A p-channel MOS pull-up transistor (62) is operably connected to the output terminal (56) to selectively drive it substantially to the internal circuit source voltage. A leakage prevention device (66), comprising a native n-channel transistor (68) with a low turn-on threshold voltage, is connected in series with the pull-up transistor (62) to prevent output terminal reverse current leakage back through the pull-up transistor (62) when the external high voltage is imposed upon the output terminal (56).

    摘要翻译： CMOS集成电路输出端子驱动器分支电路（60）在集成电路（50）的输出端子（56）提供快速响应，同时当外部高电压超过集成电路（50）的正内部电源电压时，防止反向电流泄漏 电路施加在输出端子（56）上。 输出驱动器子电路（60）还额外地在输出端提供仅在名义上低于内部电路电源电压的输出电压。 P沟道MOS上拉晶体管（62）可操作地连接到输出端（56），以选择性地将其驱动到内部电路源电压。 包括具有低导通阈值电压的天然n沟道晶体管（68）的漏电保护装置（66）与上拉晶体管（62）串联连接，以防止输出端子反向电流通过 当外部高电压施加到输出端子（56）时，上拉晶体管（62）。

    Circuit and method for memory device with defect current isolation
    8.
    发明授权
    Circuit and method for memory device with defect current isolation 失效

    公开(公告)号：US5896334A

    公开(公告)日：1999-04-20

    申请号：US911667

    申请日：1997-08-14

    申请人： Stephen L. Casper ,  David Pinney ,  Brent Keeth

    发明人： Stephen L. Casper ,  David Pinney ,  Brent Keeth

    IPC分类号： G11C17/18 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/785 ,  G11C17/18 ,  G11C29/83 ,  G11C29/832

    摘要： A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit. The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

    Open digit line array architecture for a memory array
    9.
    发明授权
    Open digit line array architecture for a memory array 有权
    用于存储器阵列的开放数字线阵列架构

    公开(公告)号：US07277310B2

    公开(公告)日：2007-10-02

    申请号：US11501144

    申请日：2006-08-07

    申请人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

    发明人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

    IPC分类号： G11C5/06

    CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

    摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

    摘要翻译： 一种用于感测由存储器单元存储的数据状态的系统和方法，包括将第一数字线和第二数字线耦合到预充电电压，并进一步将存储单元耦合到第一数字线。 除了第一和第二数字线之外的至少一个数字线被驱动到参考电压电平，并且至少一个数字线耦合到第二数字线以在第二数字线中建立参考电压。 在第一数字线和第二数字线之间感测到电压差，并且响应地锁存基于电压差的数据状态。