公开(公告)号：US09450583B2

公开(公告)日：2016-09-20

申请号：US13225718

申请日：2011-09-06

申请人： Yao-Zhong Zhang ,  Ju-Ming Chou ,  Chih-Tien Chang

发明人： Yao-Zhong Zhang ,  Ju-Ming Chou ,  Chih-Tien Chang

IPC分类号： H03K17/687 ,  H03K19/0185

CPC分类号： H03K19/018507

摘要： An input/output (IO) circuit with high voltage tolerance is provided. In an integrated circuit, the IO circuit includes a charge pump for generating a bias voltage higher than an internal operating voltage of the charge pump itself, and a switch between an external circuit and an internal circuit of the integrated circuit. When the switch conducts between the external circuit and the internal circuit, the switch provides a clamping voltage according to the bias voltage and a cross voltage of the switch, so that a voltage of the internal circuit is bounded by the clamping voltage to prevent the internal circuit from over-voltage.

摘要翻译： 提供具有高电压容差的输入/输出（IO）电路。 在集成电路中，IO电路包括用于产生高于电荷泵本身的内部工作电压的偏置电压的电荷泵以及集成电路的外部电路和内部电路之间的开关。 当开关在外部电路和内部电路之间导通时，开关根据偏置电压和开关的交叉电压提供钳位电压，使得内部电路的电压由钳位电压限制，以防止内部 电路过压。

公开(公告)号：US20120056665A1

公开(公告)日：2012-03-08

申请号：US13225718

申请日：2011-09-06

申请人： Yao-Zhong Zhang ,  Ju-Ming Chou ,  Chih-Tien Chang

发明人： Yao-Zhong Zhang ,  Ju-Ming Chou ,  Chih-Tien Chang

IPC分类号： G05F1/10

CPC分类号： H03K19/018507

摘要： An input/output (IO) circuit with high voltage tolerance is provided. In an integrated circuit, the IO circuit includes a charge pump for generating a bias voltage higher than an internal operating voltage of the charge pump itself, and a switch between an external circuit and an internal circuit of the integrated circuit. When the switch conducts between the external circuit and the internal circuit, the switch provides a clamping voltage according to the bias voltage and a cross voltage of the switch, so that a voltage of the internal circuit is bounded by the clamping voltage to prevent the internal circuit from over-voltage.

摘要翻译： 提供具有高电压容差的输入/输出（IO）电路。 在集成电路中，IO电路包括用于产生高于电荷泵本身的内部工作电压的偏置电压的电荷泵以及集成电路的外部电路和内部电路之间的开关。 当开关在外部电路和内部电路之间导通时，开关根据偏置电压和开关的交叉电压提供钳位电压，使得内部电路的电压由钳位电压限制，以防止内部 电路过压。

公开(公告)号：US20100188067A1

公开(公告)日：2010-07-29

申请号：US12692035

申请日：2010-01-22

申请人： Chih-Tien Chang ,  Ju-Ming Chou

发明人： Chih-Tien Chang ,  Ju-Ming Chou

IPC分类号： G05F3/16 ,  G09G5/00

CPC分类号： G05F1/10 ,  G09G5/006 ,  G09G2320/0693

摘要： A current calibration method and the associated control circuit are provided. The method includes: providing a predetermined voltage to the differential output for obtaining an accurate current passing through the panel resistor during a calibration procedure and, providing a driving current to the differential output according to the accurate current during a normal operation procedure.

摘要翻译： 提供了当前的校准方法和相关的控制电路。 该方法包括：向差分输出端提供预定电压，以在校准过程期间获得通过面板电阻器的精确电流，并且在正常操作过程期间根据精确电流向差分输出提供驱动电流。

公开(公告)号：US08476909B2

公开(公告)日：2013-07-02

申请号：US12692035

申请日：2010-01-22

申请人： Chih-Tien Chang ,  Ju-Ming Chou

发明人： Chih-Tien Chang ,  Ju-Ming Chou

IPC分类号： G01R35/00

CPC分类号： G05F1/10 ,  G09G5/006 ,  G09G2320/0693

摘要： A current calibration method and the associated control circuit are provided. The method includes: providing a predetermined voltage to the differential output for obtaining an accurate current passing through the panel resistor during a calibration procedure and, providing a driving current to the differential output according to the accurate current during a normal operation procedure.

摘要翻译： 提供了当前的校准方法和相关的控制电路。 该方法包括：向差分输出端提供预定电压，以在校准过程期间获得通过面板电阻器的精确电流，并且在正常操作过程期间根据精确电流向差分输出提供驱动电流。

公开(公告)号：US06777994B2

公开(公告)日：2004-08-17

申请号：US10271553

申请日：2002-10-17

申请人： Ju-Ming Chou ,  Yu-Tang Hsieh ,  Jieh-Tsorng Wu

发明人： Ju-Ming Chou ,  Yu-Tang Hsieh ,  Jieh-Tsorng Wu

IPC分类号： H03H1126

CPC分类号： H03K3/0322 ,  G06F1/04 ,  H03K5/133 ,  H03K2005/00208

摘要： To reduce the effect of the phase shift error originated from the mismatch of the delay units of the clock generator, we propose to add one more set of averaging amplifiers and averaging impedances, such as resistors, into the circuit of the clock generator. In the clock generator, outputs of all delay units connect to inputs of all averaging amplifiers respectively, and the averaging impedances connect the corresponding outputs of two adjacent averaging amplifiers, so as to form a closed loop. When a phase shift error occurs in the delay units, the averaging current through the averaging impedances will decrease the phase shift error in each stage. Specifically, the output impedance of the averaging amplifiers approaches infinite, and thus the resistance of the averaging impedances is relatively small. Therefore almost all signal currents will go through the averaging impedances, and an optimal averaging effect is achieved. In addition, we apply the simple voltage-mode phase interpolation technique to the averaging impedances for better phase resolution and more output phases. Further, utilizing the folding architecture, our proposed clock generator can output high-frequency clock signals at low-frequency operating clock.

摘要翻译： 为了减少源自时钟发生器的延迟单元不匹配的相移误差的影响，我们建议在时钟发生器的电路中增加一组平均放大器和平均阻抗（如电阻）。 在时钟发生器中，所有延迟单元的输出分别连接到所有平均放大器的输入，平均阻抗连接两个相邻平均放大器的相应输出，以形成闭环。 当在延迟单元中出现相移误差时，通过平均阻抗的平均电流将降低每个阶段的相移误差。 具体地，平均放大器的输出阻抗接近无穷大，因此平均阻抗的电阻相对较小。 因此，几乎所有的信号电流将经过平均阻抗，并且实现了最佳的平均效应。 此外，我们将简单的电压模式相位插值技术应用于平均阻抗，以获得更好的相位分辨率和更多的输出相位。 此外，利用折叠架构，我们提出的时钟发生器可以在低频工作时钟输出高频时钟信号。