公开(公告)号：US08669172B2

公开(公告)日：2014-03-11

申请号：US13488015

申请日：2012-06-04

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US07705392B2

公开(公告)日：2010-04-27

申请号：US11402972

申请日：2006-04-13

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US20060231884A1

公开(公告)日：2006-10-19

申请号：US11402972

申请日：2006-04-13

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在第一浮动栅极和第二浮动栅极之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US08211777B2

公开(公告)日：2012-07-03

申请号：US12727890

申请日：2010-03-19

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi ,  Akio Nishida ,  Shigeru Shiratake

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/7682 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

摘要翻译： 一种具有主表面的半导体衬底，在半导体衬底的主表面上彼此隔开形成的第一和第二浮置栅极，分别位于第一和第二浮置栅极上的第一和第二控制栅极，形成在第一和第二浮置栅极上的第一绝缘膜 第一控制栅极，形成在第二控制栅极上以与第一绝缘膜接触的第二绝缘膜，以及通过实现第一绝缘膜和第二绝缘体之间的接触而形成在至少在第一浮栅和第二浮栅之间的间隙部分 包括电影。 由此，可以确保非易失性半导体器件的功能，并且可以抑制浮动栅极的阈值电压的变化。

公开(公告)号：US20080303066A1

公开(公告)日：2008-12-11

申请号：US12118731

申请日：2008-05-11

申请人： Yasuaki Yonemochi ,  Hisakazu Otoi

发明人： Yasuaki Yonemochi ,  Hisakazu Otoi

IPC分类号： H01L23/538

CPC分类号： H01L27/11521 ,  H01L27/11519

摘要： A semiconductor device is provided which can suppress the deterioration of its reliability caused by liquid soaking into a gap. The semiconductor device includes plural gate electrode layers and an interlayer insulating film. The gate electrode layers are formed so as to extend in the same direction in a planar layout and each have a gate wiring portion and a contact pad portion. The interlayer insulating film is formed over the gate electrode layers and gaps so as to leave the gaps each between adjacent gate wiring portions and also between adjacent gate wiring portion and contact pad portion. A second spacing which is the distance between adjacent gate wiring portion and contact pad portion is 2.1 times or less as large as a first spacing which is the distance between adjacent gate wiring portions.

摘要翻译： 提供一种半导体器件，其可以抑制由液体浸入间隙中导致的其可靠性的劣化。 半导体器件包括多个栅电极层和层间绝缘膜。 栅极电极层形成为在平面布局中沿相同的方向延伸，并且每个具有栅极布线部分和接触焊盘部分。 层间绝缘膜形成在栅极电极层和间隙之上，以便在相邻的栅极布线部分之间以及相邻的栅极布线部分和接触焊盘部分之间留下间隙。 作为相邻的栅极配线部与接触焊盘部之间的距离的第二间隔是与相邻的栅极配线部之间的距离的第一间隔的2.1倍以下。