公开(公告)号：US20080290396A1

公开(公告)日：2008-11-27

申请号：US12125546

申请日：2008-05-22

申请人： Yasuhiko MATSUNAGA ,  Yuji Takeuchi ,  Takashi Shigeoka

发明人： Yasuhiko MATSUNAGA ,  Yuji Takeuchi ,  Takashi Shigeoka

IPC分类号： H01L29/00

CPC分类号： H01L27/105 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory according to an aspect of this invention comprises a semiconductor substrate which includes a memory cell array region and an interconnect line region adjoining the memory cell array region, memory cells which are provided in the memory cell array region, contact plugs which are provided in the interconnect line region, and control gate lines which are provided so as to extend from the interconnect line region to the memory cell array region and which connect the contact plugs with the memory cells, wherein the control gate lines provided in the memory cell array region include metal silicide and the control gate lines provided in the interconnect line region include no metal silicide at any part of the interconnect line region.

摘要翻译： 根据本发明的一个方面的半导体存储器包括半导体衬底，其包括存储单元阵列区域和与存储单元阵列区域相邻的互连线区域，设置在存储单元阵列区域中的存储单元，提供的接触插头 以及控制栅极线，其设置为从互连线区域延伸到存储单元阵列区域，并将接触插头与存储器单元连接，其中设置在存储单元阵列中的控制栅极线 区域包括金属硅化物，并且设置在互连线区域中的控制栅极线在互连线区域的任何部分不包括金属硅化物。

公开(公告)号：US20120099374A1

公开(公告)日：2012-04-26

申请号：US13277623

申请日：2011-10-20

申请人： Yasuhiko MATSUNAGA

发明人： Yasuhiko MATSUNAGA

IPC分类号： G11C16/04

CPC分类号： H01L27/11529 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/11519 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device includes a substrate including device regions extending in a first direction, a memory cell array region including a plurality of memory cells disposed on the device regions, bit lines extending in the first direction, a sense amplifier circuit connected to ends of the bit lines, and bit line contacts connecting device regions to bit lines. The memory cell array region includes first to N-th regions where N is an integer of two or more, and a K-th region is located at a greater distance from the sense amplifier circuit than a (K−1)-th region, where K is an arbitrary integer of 2 to N. Contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−1)-th region, each device region having constant width in the memory cell array region.

摘要翻译： 一种非易失性半导体存储器件，包括：基板，包括沿第一方向延伸的器件区域;存储单元阵列区域，包括设置在器件区域上的多个存储单元;沿第一方向延伸的位线;连接到 位线和位线接触将器件区域连接到位线。 存储单元阵列区域包括第一至第N区域，其中N是两个或更多个的整数，并且第K个区域位于距离读出放大器电路比第（K-1）个区域更大的距离处， 其中K是2至N的任意整数。在第K区中位线接触的接触电阻低于第（K-1）区中的位线接触的接触电阻，每个器件区具有恒定 存储单元阵列区域的宽度。

公开(公告)号：US20100176422A1

公开(公告)日：2010-07-15

申请号：US12649822

申请日：2009-12-30

申请人： Koichi FUKUDA ,  Dai NAKAMURA ,  Yasuhiko MATSUNAGA

发明人： Koichi FUKUDA ,  Dai NAKAMURA ,  Yasuhiko MATSUNAGA

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval.

摘要翻译： 半导体存储器件包括半导体衬底; 所述存储单元阵列包括能够电存储数据的多个存储单元;存储单元阵列， 感测放大器，被配置为检测存储在所述存储器单元中的至少一个中的数据; 电池源驱动器，电连接到存储器单元的源极端子，并且被配置为向存储器单元的至少一个源极侧端子提供源极电位; 第一布线，被配置为电连接所述存储单元的至少一个源极端子和所述单元源驱动器; 以及形成在与所述第一布线相同的布线层中的第二布线，所述第二布线与所述第一布线绝缘并且电连接到所述读出放大器，其中所述第一布线和所述第二布线具有设置在所述第一布线的多个通孔 预定间隔。

公开(公告)号：US20090286526A1

公开(公告)日：2009-11-19

申请号：US12434412

申请日：2009-05-01

申请人： Yasuhiko MATSUNAGA

发明人： Yasuhiko MATSUNAGA

IPC分类号： H04M11/00 ,  H04L12/26 ,  H04W24/00

CPC分类号： H04W24/00 ,  G01S2205/007 ,  H04L43/0847 ,  H04W64/00

摘要： A radio quality degradation prediction system includes a wireless terminal and a monitoring server. The wireless terminal includes a positioning unit that determines a position of the wireless terminal and notifies the monitoring server of movement history of the wireless terminal via a wireless network, and a user notification unit that gives a warning to a user upon receiving a radio quality degradation alert at the wireless terminal. The monitoring server includes a future position prediction unit that predicts a future position of the wireless terminal based on the movement history of the wireless terminal, a radio propagation prediction unit that estimates radio quality in a service coverage area by using a radiowave propagation simulator, and a quality degradation prediction unit that predicts degradation of radio quality at the future position of the wireless terminal and transmits a radio quality degradation alert to the wireless terminal.

摘要翻译： 无线质量劣化预测系统包括无线终端和监视服务器。 无线终端包括：定位单元，其确定无线终端的位置，并且经由无线网络向监视服务器通知无线终端的移动历史;以及用户通知单元，其在接收到无线电质量劣化时向用户发出警告 在无线终端提醒。 监视服务器包括：未来位置预测单元，其基于无线终端的移动历史来预测无线终端的未来位置;无线传播预测单元，其使用无线电波传播模拟器来估计服务覆盖区域中的无线质量;以及 质量劣化预测单元，其预测无线终端的未来位置的无线电质量的劣化，并向无线终端发送无线质量劣化警报。

公开(公告)号：US20120201159A1

公开(公告)日：2012-08-09

申请号：US13366032

申请日：2012-02-03

申请人： Motoki MORITA ,  Yasuhiko MATSUNAGA

发明人： Motoki MORITA ,  Yasuhiko MATSUNAGA

IPC分类号： H04W72/08 ,  H04W24/00

CPC分类号： H04W72/082 ,  H04W16/10 ,  H04W52/244 ,  H04W84/045 ,  H04W88/08

摘要： A base station includes a radio communication unit, a resource adjustment unit, a resource division unit and a detection unit. The resource adjustment unit determines radio resources to be allocated to a downlink communication from a radio resource region shared with another base station. The resource division unit limits, to a first radio resource segment which is a part of the radio resource region, radio resources in response to estimating that communication quality of the downlink communication using the limited first radio resource segment is improved over the communication quality of the first downlink communication when using the entire range of the radio resource region that is shared with the other base station. The detection unit detects execution of resource division by the other base station for limiting radio resources used for another downlink communication between the other base station and a mobile station to a second radio resource segment.

摘要翻译： 基站包括无线电通信单元，资源调整单元，资源划分单元和检测单元。 资源调整单元从与另一基站共享的无线资源区域确定要分配给下行链路通信的无线资源。 所述资源分割单元对作为所述无线资源区域的一部分的第一无线资源段限制无线资源，所述无线资源响应于使用所述受限的第一无线资源段的所述下行通信的通信质量相对于 当使用与另一个基站共享的无线电资源区域的整个范围时的第一下行链路通信。 检测单元检测另一基站的资源划分的执行，用于将用于另一基站与移动台之间的另一下行链路通信的无线资源限制到第二无线电资源段。

公开(公告)号：US20110018046A1

公开(公告)日：2011-01-27

申请号：US12900110

申请日：2010-10-07

申请人： Hiroyuki KUTSUKAKE ,  Yasuhiko MATSUNAGA ,  Shoichi MIYAZAKI

发明人： Hiroyuki KUTSUKAKE ,  Yasuhiko MATSUNAGA ,  Shoichi MIYAZAKI

IPC分类号： H01L29/68

CPC分类号： H01L23/485 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的第一表面上沿着第一方向形成两个第一栅电极和在每个第一栅电极下夹着沟道区的源/漏区，形成第一层间绝缘层以填充 在所述第一栅电极之间的区域中，降低所述第一层间绝缘层的顶部，在所述第一层间绝缘层上沉积第二层间绝缘层和所述第一栅电极，使所述第二层间绝缘层的表面平坦化，以及形成互连 层和第一层间绝缘层和第二层间绝缘层中的接触塞，使得接触插塞与互连层和源极/漏极区之一接触。

公开(公告)号：US20100044769A1

公开(公告)日：2010-02-25

申请号：US12610022

申请日：2009-10-30

申请人： Hiroyuki KUTSUKAKE ,  Yasuhiko MATSUNAGA ,  Shoichi MIYAZAKI

发明人： Hiroyuki KUTSUKAKE ,  Yasuhiko MATSUNAGA ,  Shoichi MIYAZAKI

IPC分类号： H01L29/78

CPC分类号： H01L23/485 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的第一表面上沿着第一方向形成两个第一栅电极和在每个第一栅电极下夹着沟道区的源/漏区，形成第一层间绝缘层以填充 在所述第一栅电极之间的区域中，降低所述第一层间绝缘层的顶部，在所述第一层间绝缘层上沉积第二层间绝缘层和所述第一栅电极，使所述第二层间绝缘层的表面平坦化，以及形成互连 层和第一层间绝缘层和第二层间绝缘层中的接触塞，使得接触插塞与互连层和源极/漏极区之一接触。

公开(公告)号：US20090239365A1

公开(公告)日：2009-09-24

申请号：US12480383

申请日：2009-06-08

申请人： Yasuhiko MATSUNAGA

发明人： Yasuhiko MATSUNAGA

IPC分类号： H01L21/71 ,  H01L21/28

CPC分类号： H01L27/115 ,  H01L27/11526 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory that allows simultaneous implementation of high performance transistors in a low-voltage circuit region and transistors with high withstand voltages in a high-voltage circuit region. The nonvolatile semiconductor memory includes a cell array region that comprises aligned memory cell transistors, each including a control gate electrode, which includes a metal silicide film, an inter-gate insulating film below the control gate electrode, a floating gate electrode below the inter-gate insulating film, and a tunnel insulating film under the floating gate electrode; a high-voltage circuit region arranged in a periphery of the cell array region and including a high voltage transistor, which includes a first gate insulating film thicker than the tunnel insulating film; and a low-voltage circuit region that is arranged in a different position than the high-voltage circuit region arranged in the periphery of the cell array region and that includes a low-voltage transistor, which includes a gate electrode and a second gate insulating film thinner than the first gate insulating film below the gate electrode.

摘要翻译： 一种非易失性半导体存储器，其允许在高压电路区域中同时实现低电压电路区域中的高性能晶体管和在高压电路区域中具有高耐受电压的晶体管。 非易失性半导体存储器包括：单元阵列区域，其包括排列的存储单元晶体管，每个存储单元晶体管包括控制栅电极，其包括金属硅化物膜，位于控制栅极电极下方的栅极间绝缘膜， 栅极绝缘膜和在浮栅电极下方的隧道绝缘膜; 布置在电池阵列区域的外围并包括高压晶体管的高压电路区域，其包括比隧道绝缘膜厚的第一栅极绝缘膜; 以及低压电路区域，其布置在与布置在电池阵列区域周围的高电压电路区域不同的位置，并且包括低电压晶体管，该低压晶体管包括栅极电极和第二栅极绝缘膜 比栅电极下方的第一栅绝缘膜薄。

公开(公告)号：US20090021982A1

公开(公告)日：2009-01-22

申请号：US12175008

申请日：2008-07-17

申请人： Yasuhiko MATSUNAGA ,  Fumitaka ARAI

发明人： Yasuhiko MATSUNAGA ,  Fumitaka ARAI

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C11/5635 ,  G11C16/16 ,  G11C2211/565

摘要： A semiconductor memory device includes a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first and second select transistors, a source line, and a bit line, wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元串，每个存储单元串包括多个存储单元和第一虚单元，该第一虚单元具有在一端串联连接的电流通路和另一端，多个第一 以及第二选择晶体管，源极线和位线，其中第一虚设单元设置在源极侧，使得其电流通路的一端和另一端连接在第一选择晶体管和存储单元之间 并且第一虚拟单元的阈值电压高于中性阈值电压。