公开(公告)号：US4835705A

公开(公告)日：1989-05-30

申请号：US014374

申请日：1987-02-10

申请人： Yasuhiro Fujino ,  Masayuki Terai ,  Tomoyoshi Noda ,  Yoshihide Ajioka

发明人： Yasuhiro Fujino ,  Masayuki Terai ,  Tomoyoshi Noda ,  Yoshihide Ajioka

IPC分类号： H01L21/3205 ,  G06F17/50 ,  H01L21/82 ,  H01L23/52 ,  H01L27/118

CPC分类号： G06F17/5077

摘要： The present invention provides an interconnection area decision processor for deciding vertical widths of areas employed for interconnection of a gate array. The interconnection area decision processor predicts which interconnection area each signal net passes on the basis of previously created data on cell arrangement and data on arrangement of transistor rows on a chip to estimate interconnection congestion per channel on the basis of the result of prediction and decide the number of transistor rows to be assigned to each channel on the basis of the estimated interconnection congestion, thereby to create data on the vertical width of each channel. Thus, density of integration can be improved by increasing the number of tracks of channels having large numbers of interconnections and decreasing the number of tracks of channels having small numbers of interconnections.

摘要翻译： 本发明提供了一种用于确定用于门阵列互连的区域的垂直宽度的互连区决定处理器。 互连区域判定处理器根据先前创建的关于单元布置的数据和芯片上的晶体管行的布置数据来预测每个信号网络哪个互连区域通过哪个互连区域，以基于预测结果估计每个信道的互连拥塞，并且决定 基于估计的互连拥塞来分配给每个信道的晶体管行数，从而在每个通道的垂直宽度上创建数据。 因此，通过增加具有大量互连的通道的轨道数量并减少具有少量互连的通道的轨道数量，可以提高积分密度。

公开(公告)号：US5859449A

公开(公告)日：1999-01-12

申请号：US931479

申请日：1997-09-16

申请人： Hiroyuki Kobayashi ,  Shuichi Ichikawa ,  Yoshihide Ajioka

发明人： Hiroyuki Kobayashi ,  Shuichi Ichikawa ,  Yoshihide Ajioka

IPC分类号： H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10

CPC分类号： H01L27/0207

摘要： A semiconductor integrated circuit in which adjacent terminals are formed by using contacts for connecting two metal layers or formed by using any of the metal layers so as to be disposed away from each other with an interval equal to larger than one wiring interval in the vertical and the horizontal directions, for example, diagonally or obliquely in a cell.

摘要翻译： 一种半导体集成电路，其中通过使用用于连接两个金属层的触点或通过使用任何金属层形成的相邻端子以彼此远离彼此设置，间隔等于大于垂直于一个布线间隔的间隔，以及 水平方向，例如，在单元格中对角或倾斜。

公开(公告)号：US06504186B2

公开(公告)日：2003-01-07

申请号：US09090379

申请日：1998-06-04

申请人： Toshiki Kanamoto ,  Yoshihide Ajioka ,  Yukihiko Shimazu ,  Hideyuki Hamada

发明人： Toshiki Kanamoto ,  Yoshihide Ajioka ,  Yukihiko Shimazu ,  Hideyuki Hamada

IPC分类号： H01L2710

CPC分类号： H01L27/11803

摘要： In a semiconductor device provided with a plurality of standard cells each comprising an input terminal and MOS transistors, a diffused region having a substantially negligibly small resistance is formed in a semiconductor substrate, and the input terminal of the standard cell and gates of the MOS transistors are connected through the diffused region. Also, a diffused region is formed under the input terminal in the substrate, and the input terminal is connected to the diffused region. In a modification, another standard cell is formed by forming a diffused region and a metal layer connected to the diffused region on the substrate, and the another standard cell is connected to the input terminal.

摘要翻译： 在设置有包括输入端子和MOS晶体管的多个标准单元的半导体器件中，在半导体衬底中形成具有基本可忽略的小电阻的扩散区域，并且标准单元的输入端子和MOS晶体管的栅极 通过扩散区连接。 此外，在基板的输入端子的下方形成扩散区域，输入端子与扩散区域连接。 在变形例中，通过形成扩散区域和连接到基板上的扩散区域的金属层来形成另一个标准单元，另一个标准单元连接到输入端子。