公开(公告)号：US09105247B2

公开(公告)日：2015-08-11

申请号：US12848717

申请日：2010-08-02

申请人： Yi-Fan Lin ,  Mu-Lin Tung ,  Chao-Ching Hsu

发明人： Yi-Fan Lin ,  Mu-Lin Tung ,  Chao-Ching Hsu

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： G09G3/3614 ,  G09G2300/0426 ,  G09G2330/021

摘要： A display device includes multiple first data lines, multiple second data lines, multiple pixel columns, at least a first charge sharing switch circuit and at least a second charge sharing switch circuit. The second data lines are alternately arranged with the first data lines. Each of the pixel columns includes multiple first pixels and multiple second pixels. The first pixels of each of the pixel columns are coupled to one of the first data lines, and the second pixels of each of the pixel columns are coupled to one of the second data lines. The first charge sharing switch circuit each is electrically coupled to at least a part of the first data lines. The second charge sharing switch circuit each is electrically coupled to at least a part of the second data lines. A display device driving method and a source driving circuit also are provided.

摘要翻译： 显示装置包括多个第一数据线，多个第二数据线，多个像素列，至少第一电荷共享开关电路和至少第二电荷共享开关电路。 第二数据线与第一数据线交替布置。 每个像素列包括多个第一像素和多个第二像素。 每个像素列的第一像素被耦合到第一数据线中的一个，并且每个像素列的第二像素被耦合到第二数据线之一。 第一电荷共享开关电路各自电耦合到第一数据线的至少一部分。 第二电荷共享开关电路各自电耦合到第二数据线的至少一部分。 还提供了一种显示装置驱动方法和源极驱动电路。

公开(公告)号：US20110248985A1

公开(公告)日：2011-10-13

申请号：US12848717

申请日：2010-08-02

申请人： Yi-Fan LIN ,  Mu-Lin Tung ,  Chao-Ching Hsu

发明人： Yi-Fan LIN ,  Mu-Lin Tung ,  Chao-Ching Hsu

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： G09G3/3614 ,  G09G2300/0426 ,  G09G2330/021

摘要： A display device includes multiple first data lines, multiple second data lines, multiple pixel columns, at least a first charge sharing switch circuit and at least a second charge sharing switch circuit. The second data lines are alternately arranged with the first data lines. Each of the pixel columns includes multiple first pixels and multiple second pixels. The first pixels of each of the pixel columns are coupled to one of the first data lines, and the second pixels of each of the pixel columns are coupled to one of the second data lines. The first charge sharing switch circuit each is electrically coupled to at least a part of the first data lines. The second charge sharing switch circuit each is electrically coupled to at least a part of the second data lines. A display device driving method and a source driving circuit also are provided.

摘要翻译： 显示装置包括多个第一数据线，多个第二数据线，多个像素列，至少第一电荷共享开关电路和至少第二电荷共享开关电路。 第二数据线与第一数据线交替布置。 每个像素列包括多个第一像素和多个第二像素。 每个像素列的第一像素被耦合到第一数据线中的一个，并且每个像素列的第二像素被耦合到第二数据线之一。 第一电荷共享开关电路各自电耦合到第一数据线的至少一部分。 第二电荷共享开关电路各自电耦合到第二数据线的至少一部分。 还提供了一种显示装置驱动方法和源极驱动电路。

公开(公告)号：US08830155B2

公开(公告)日：2014-09-09

申请号：US12609573

申请日：2009-10-30

申请人： Chao-Ching Hsu ,  Jen-Chieh Chen ,  Mu-Lin Tung

发明人： Chao-Ching Hsu ,  Jen-Chieh Chen ,  Mu-Lin Tung

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3607 ,  G09G2310/0213 ,  G09G2310/0297 ,  G09G2320/0247 ,  G09G2320/0686 ,  G09G2330/021 ,  G09G2360/16

摘要： The present invention in one aspect relates to a source driver for driving a display panel to display an image data in an adaptive column inversion. In one embodiment, the source driver includes a data processing unit having a logic circuit adapted for determining N most-significant bits (MSBs) of image data signals of two neighboring data lines, such that when all of the N MSBs are equal to 1 or 0, the output of the logic circuit is 1, otherwise, the output of the logic circuit is 0, and a MUX coupled to the data processing unit and adapted for receiving a frame polarity control signal, FramePOL, and a pixel polarity control signal, XPOL, and selectively outputting the frame polarity control signal FramePOL when the output of the logic circuit is 1, or the pixel polarity control signal POL when the output of the logic circuit is 0, as a polarity control signal, POL.

摘要翻译： 本发明一方面涉及用于驱动显示面板以在自适应列反转中显示图像数据的源驱动器。 在一个实施例中，源驱动器包括具有逻辑电路的数据处理单元，该逻辑电路适于确定两个相邻数据线的图像数据信号的N个最高有效位（MSB），使得当所有N个MSB都等于1或 0，逻辑电路的输出为1，否则逻辑电路的输出为0，MUX耦合到数据处理单元，适用于接收帧极性控制信号FramePOL和像素极性控制信号， 并且当逻辑电路的输出为1时选择性地输出帧极性控制信号FramePOL，或者当逻辑电路的输出为0时的像素极性控制信号POL作为极性控制信号POL。

公开(公告)号：US20110102471A1

公开(公告)日：2011-05-05

申请号：US12609573

申请日：2009-10-30

申请人： Chao-Ching Hsu ,  Jen-Chieh Chen ,  Mu-Lin Tung

发明人： Chao-Ching Hsu ,  Jen-Chieh Chen ,  Mu-Lin Tung

IPC分类号： G09G5/10 ,  G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3607 ,  G09G2310/0213 ,  G09G2310/0297 ,  G09G2320/0247 ,  G09G2320/0686 ,  G09G2330/021 ,  G09G2360/16

摘要： The present invention in one aspect relates to a source driver for driving a display panel to display an image data in an adaptive column inversion. In one embodiment, the source driver includes a data processing unit having a logic circuit adapted for determining N most-significant bits (MSBs) of image data signals of two neighboring data lines, such that when all of the N MSBs are equal to 1 or 0, the output of the logic circuit is 1, otherwise, the output of the logic circuit is 0, and a MUX coupled to the data processing unit and adapted for receiving a frame polarity control signal, FramePOL, and a pixel polarity control signal, XPOL, and selectively outputting the frame polarity control signal FramePOL when the output of the logic circuit is 1, or the pixel polarity control signal POL when the output of the logic circuit is 0, as a polarity control signal, POL.

摘要翻译： 本发明一方面涉及用于驱动显示面板以在自适应列反转中显示图像数据的源驱动器。 在一个实施例中，源驱动器包括具有逻辑电路的数据处理单元，该逻辑电路适于确定两个相邻数据线的图像数据信号的N个最高有效位（MSB），使得当所有N个MSB都等于1或 0，逻辑电路的输出为1，否则逻辑电路的输出为0，MUX耦合到数据处理单元，适用于接收帧极性控制信号FramePOL和像素极性控制信号， 并且当逻辑电路的输出为1时选择性地输出帧极性控制信号FramePOL，或者当逻辑电路的输出为0时的像素极性控制信号POL作为极性控制信号POL。

公开(公告)号：US08436801B2

公开(公告)日：2013-05-07

申请号：US12684908

申请日：2010-01-09

申请人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

发明人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

IPC分类号： G09G3/36

CPC分类号： H03K19/0175 ,  G09G3/3677 ,  G09G2310/0289 ,  G09G2330/023

摘要： A level shift circuit includes a control logic circuit, a plurality of level shift output buffers and a plurality of charge sharing circuits. The control logic circuit receives input clock pulse signals and a charge sharing signal and acquires voltage level information of each received signal. Each output buffer amplifies a corresponding input clock pulse signal and determines whether to output a signal according to the acquired information of the charge sharing signal. Each charge sharing circuit determines whether to be turned on according to the acquired information of a corresponding input clock pulse signal. When a charge sharing circuit is turned on, the output terminal of a corresponding output buffer and a predetermined voltage level are coupled to each other by the charge sharing circuit, so as to perform the charge sharing operation. Furthermore, a corresponding liquid crystal display device and a corresponding charge sharing method are also provided.

摘要翻译： 电平移位电路包括控制逻辑电路，多个电平移位输出缓冲器和多个电荷共享电路。 控制逻辑电路接收输入时钟脉冲信号和电荷共享信号，并获取每个接收信号的电压电平信息。 每个输出缓冲器放大对应的输入时钟脉冲信号，并根据获取的电荷共享信号的信息确定是否输出信号。 每个电荷共享电路根据所获取的相应输入时钟脉冲信号的信息确定是否被接通。 当电荷共享电路接通时，相应的输出缓冲器的输出端和预定的电压电平通过电荷共享电路彼此耦合，从而进行电荷共享操作。 此外，还提供了相应的液晶显示装置和相应的电荷共享方法。

公开(公告)号：US07750715B2

公开(公告)日：2010-07-06

申请号：US12315189

申请日：2008-11-28

申请人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

发明人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

IPC分类号： G06F1/04

CPC分类号： G09G3/3611 ,  G09G3/3677 ,  G09G2330/023 ,  G11C7/222 ,  G11C19/00 ,  H03K19/0013 ,  H03K19/0016

摘要： A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.

摘要翻译： 时钟发生电路具有两个输出端，以分别响应于第一和第二输入信号提供第一时钟信号和第二时钟信号。 当第一时钟信号为高电平一段时间时，电荷存储部件用于将一些电荷从第一输出端传送到电荷存储部件，并且当电荷存储部件的电荷从电荷存储部件传送到第二输出端时， 第二个时钟信号为低电平。 在时钟周期的不同时间段，当第二时钟信号为高电平一段时间时，电荷存储部件用于将一些电荷从第二输出端传送到电荷存储部件，并将电荷从 当第一时钟信号为低时，电荷存储部件到第一输出端。

公开(公告)号：US20100134172A1

公开(公告)日：2010-06-03

申请号：US12315189

申请日：2008-11-28

申请人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

发明人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Chung-Shen Cheng

IPC分类号： G06F1/06

CPC分类号： G09G3/3611 ,  G09G3/3677 ,  G09G2330/023 ,  G11C7/222 ,  G11C19/00 ,  H03K19/0013 ,  H03K19/0016

摘要： A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.

摘要翻译： 时钟发生电路具有两个输出端，以分别响应于第一和第二输入信号提供第一时钟信号和第二时钟信号。 当第一时钟信号为高电平一段时间时，电荷存储部件用于将一些电荷从第一输出端传送到电荷存储部件，并且当电荷存储部件的电荷从电荷存储部件传送到第二输出端时， 第二个时钟信号为低电平。 在时钟周期的不同时间段，当第二时钟信号为高电平一段时间时，电荷存储部件用于将一些电荷从第二输出端传送到电荷存储部件，并将电荷从 当第一时钟信号为低时，电荷存储部件到第一输出端。

公开(公告)号：US08325126B2

公开(公告)日：2012-12-04

申请号：US12647560

申请日：2009-12-28

申请人： Hsiao-Chung Cheng ,  Chao-Ching Hsu ,  Mu-Lin Tung

发明人： Hsiao-Chung Cheng ,  Chao-Ching Hsu ,  Mu-Lin Tung

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3611 ,  G09G2310/067 ,  G09G2320/0219 ,  G09G2330/023 ,  G11C19/28

摘要： A liquid crystal display includes a gate driver, a control circuit and a charge-sharing circuit. The control circuit provides a charge-sharing signal according to the parasitic capacitances at a first output end and a second output end in the gate driver. The charge-sharing circuit generates a third clock signal and a fourth clock signal by performing charge-sharing on a first clock signal and a second clock signal according to the charge-sharing signal. The third clock signal includes a signal falling edge which descends from a high level to a first level, and the fourth clock signal includes a signal falling edge which descends from the high level to a second level. The gate driver outputs a first gate driving signal and a second gate driving signal respectively at the first and the second output end according the third or the fourth clock signal.

摘要翻译： 液晶显示器包括栅极驱动器，控制电路和电荷共享电路。 控制电路根据栅极驱动器中的第一输出端和第二输出端处的寄生电容提供电荷共享信号。 电荷共享电路通过根据电荷共享信号在第一时钟信号和第二时钟信号上执行电荷共享来产生第三时钟信号和第四时钟信号。 第三时钟信号包括从高电平下降到第一电平的信号下降沿，并且第四时钟信号包括从高电平下降到第二电平的信号下降沿。 栅极驱动器根据第三或第四时钟信号在第一和第二输出端分别输出第一栅极驱动信号和第二栅极驱动信号。

公开(公告)号：US20100245333A1

公开(公告)日：2010-09-30

申请号：US12577700

申请日：2009-10-12

申请人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Jen-Chieh Chen

发明人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Jen-Chieh Chen

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G2300/0426 ,  G09G2310/067 ,  G09G2320/0219 ,  G09G2320/0247

摘要： A method for driving a liquid crystal display adjusts the falling edges of the gate driving signals for reducing image flicker. A first gate driving signal falls from a high level to a first level at the signal falling edge. A second gate driving signal falls from the high level to a second level at the signal falling edge. When the parasitic capacitance of a first pixel is larger than that of a second pixel, the first level is lower than the second level; when the parasitic capacitance of the first pixel is substantially the same as that of the second pixel, the first level is the same as the second level; when the parasitic capacitance of the first pixel is smaller than that of the second pixel, the first level is higher than the second level.

摘要翻译： 用于驱动液晶显示器的方法调节用于降低图像闪烁的栅极驱动信号的下降沿。 第一栅极驱动信号在信号下降沿从高电平下降到第一电平。 第二栅极驱动信号在信号下降沿从高电平下降到第二电平。 当第一像素的寄生电容大于第二像素的寄生电容时，第一电平低于第二电平; 当第一像素的寄生电容基本上与第二像素的寄生电容相同时，第一电平与第二电平相同; 当第一像素的寄生电容小于第二像素的寄生电容时，第一电平高于第二电平。

公开(公告)号：US08253673B2

公开(公告)日：2012-08-28

申请号：US12577700

申请日：2009-10-12

申请人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Jen-Chieh Chen

发明人： Chao-Ching Hsu ,  Mu-Lin Tung ,  Jen-Chieh Chen

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G2300/0426 ,  G09G2310/067 ,  G09G2320/0219 ,  G09G2320/0247

摘要： A method for driving a liquid crystal display adjusts the falling edges of the gate driving signals for reducing image flicker. A first gate driving signal falls from a high level to a first level at the signal falling edge. A second gate driving signal falls from the high level to a second level at the signal falling edge. When the parasitic capacitance of a first pixel is larger than that of a second pixel, the first level is lower than the second level; when the parasitic capacitance of the first pixel is substantially the same as that of the second pixel, the first level is the same as the second level; when the parasitic capacitance of the first pixel is smaller than that of the second pixel, the first level is higher than the second level.

摘要翻译： 用于驱动液晶显示器的方法调节用于降低图像闪烁的栅极驱动信号的下降沿。 第一栅极驱动信号在信号下降沿从高电平下降到第一电平。 第二栅极驱动信号在信号下降沿从高电平下降到第二电平。 当第一像素的寄生电容大于第二像素的寄生电容时，第一电平低于第二电平; 当第一像素的寄生电容基本上与第二像素的寄生电容相同时，第一电平与第二电平相同; 当第一像素的寄生电容小于第二像素的寄生电容时，第一电平高于第二电平。