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    Integrated circuit package having inductance loop formed from a bridge interconnect
    1.
    发明授权
    Integrated circuit package having inductance loop formed from a bridge interconnect 有权
    集成电路封装，其具有由桥互连形成的电感环路

    公开(公告)号：US07071535B2

    公开(公告)日：2006-07-04

    申请号：US10927152

    申请日：2004-08-27

    申请人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonban Park ,  Kyeongho Lee

    发明人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonban Park ,  Kyeongho Lee

    IPC分类号： H01L29/00 ,  H03B7/14

    CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

    摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一引线和将芯片上的第二接合焊盘连接到第二引线的第二引线形成 封装的I / O引脚。 为了完成电感环路，第一和第二I / O引脚通过引脚之间的导电桥连接。 可以通过使I / O引脚具有单一结构来形成桥。 在另一个实施例中，桥由位于封装衬底的表面上或在该衬底内的金属化层形成。 I / O引脚优选为彼此相邻的引脚; 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

    Integrated circuit package having inductance loop formed from a bridge interconnect
    3.
    发明申请
    Integrated circuit package having inductance loop formed from a bridge interconnect 有权
    集成电路封装，其具有由桥互连形成的电感环路

    公开(公告)号：US20050045988A1

    公开(公告)日：2005-03-03

    申请号：US10927152

    申请日：2004-08-27

    申请人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H01L20060101 ,  H01L23/64 ,  H01L29/00 ,  H03B5/12

    CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

    摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一引线和将芯片上的第二接合焊盘连接到第二引线的第二引线形成 封装的I / O引脚。 为了完成电感环路，第一和第二I / O引脚通过引脚之间的导电桥连接。 可以通过使I / O引脚具有单一结构来形成桥。 在另一个实施例中，桥由位于封装衬底的表面上或在该衬底内的金属化层形成。 I / O引脚优选为彼此相邻的引脚; 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

    Integrated circuit package having an inductance loop formed from a multi-loop configuration
    4.
    发明授权
    Integrated circuit package having an inductance loop formed from a multi-loop configuration 有权
    具有由多回路配置形成的电感回路的集成电路封装

    公开(公告)号：US07768097B2

    公开(公告)日：2010-08-03

    申请号：US10927012

    申请日：2004-08-27

    申请人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H01L23/58 ,  H01L29/00 ,  H03B7/06

    CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

    摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一和第二引线形成，以及连接芯片上的第二焊盘的第三和第四引线 到包的第二个I / O引脚。 为了完成电感线圈，第一和第二I / O引脚通过引脚之间的第三根导体连接。 第三导体可以包括一个或多个接合线，并且I / O引脚优选地彼此相邻。 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 在另一个实施例中，通过使I / O引脚具有整体结构来建立第一和第二I / O引脚之间的连接。 在另一个实施例中，第一和第二I / O引脚之间的连接由位于封装基板的表面上或者在该基板内的金属化层建立。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

    Sample and hold type fractional-N frequency synthesizer
    5.
    发明授权
    Sample and hold type fractional-N frequency synthesizer 有权
    采样和保持型小数N频率合成器

    公开(公告)号：US06704383B2

    公开(公告)日：2004-03-09

    申请号：US09940808

    申请日：2001-08-29

    申请人： Jeongwoo Lee ,  Yido Koo ,  Kang Yoon Lee ,  Eunseok Song ,  Hyungki Huh ,  Joonbae Park ,  Kyeongho Lee

    发明人： Jeongwoo Lee ,  Yido Koo ,  Kang Yoon Lee ,  Eunseok Song ,  Hyungki Huh ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H03D324

    CPC分类号： H03L7/0898 ,  H03L7/087 ,  H03L7/095 ,  H03L7/1976

    摘要： A phase-locked loop (PLL) fractional-N type frequency synthesizer incorporates a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. Further, the synthesizer can incorporate fractional spur compensation circuitry to compensate charge pump ripple whenever a charge pump operates. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes while a control voltage is stably maintained for the voltage controlled oscillator.

    摘要翻译： 锁相环（PLL）小数N型频率合成器包含采样保持电路。 合成器可以通过消除环路滤波器来减小电路尺寸。 此外，合成器可以包括分数支路补偿电路，以便在电荷泵工作时补偿电荷泵波动。 合成器或分数N型PLL可以使用分频器和耦合到采样和保持电路的至少两个相位检测器。 锁定检测电路可以最初确定采样和保持电路的参考电压。 此外，分数补偿是动态地实现的，并且以对于环境变化是稳健的方式实现，同时稳定地维持用于压控振荡器的控制电压。

    System and method for tuning a frequency generator using an LC oscillator
    7.
    发明授权
    System and method for tuning a frequency generator using an LC oscillator 有权
    使用LC振荡器调谐频率发生器的系统和方法

    公开(公告)号：US07512390B2

    公开(公告)日：2009-03-31

    申请号：US11057414

    申请日：2005-02-15

    申请人： Kang Yoon Lee ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    发明人： Kang Yoon Lee ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

    IPC分类号： H04B7/00 ,  H04B1/181

    CPC分类号： H03L7/085 ,  H03L7/099 ,  H03L7/1976 ,  H03L7/199

    摘要： An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal. In one embodiment, coarse tuning and lead-lag detection is performed more accurately to allow the size of the varactors to become significantly reduced compared with other circuits which have been proposed.

    摘要翻译： LC-VCO包括输出频率信号的多谐振荡器，将频率信号调谐第一量的微调电路，将频率信号调谐第二量的粗调谐电路，以及控制电路， 粗调电路。 粗调谐电路由一个或多个电容阵列形成，并且微调电路由一个或多个变容二极管形成。 电容阵列优选地由数字信号控制，其中每个位选择性地将相应的电容器耦合到多谐振荡器。 模拟信号控制变容二极管的值。 电容阵列和变容二极管对多谐振荡器中的感应器充电和放电，以调谐频率信号。 VCO可以并入在锁相环中，其中电容器可被分配不同的权重和/或冗余值来调谐输出频率信号。 在一个实施例中，与已经提出的其他电路相比，更精确地执行粗调和超前滞后检测，以允许变容二极管的尺寸显着降低。

    ANALOG-TO-DIGITAL SIGNAL CONVERSION METHOD AND APPARATUS THEREFOR
    8.
    发明申请
    ANALOG-TO-DIGITAL SIGNAL CONVERSION METHOD AND APPARATUS THEREFOR 失效
    模拟数字信号转换方法及其设备

    公开(公告)号：US20140009317A1

    公开(公告)日：2014-01-09

    申请号：US13620352

    申请日：2012-09-14

    申请人： Yoo Sam NA ,  Kang Yoon Lee ,  Young Gun Pu ,  Hyung Gu Park ,  Hong Jin Kim ,  Yoo Hwan Kim ,  Dong Su Lee

    发明人： Yoo Sam NA ,  Kang Yoon Lee ,  Young Gun Pu ,  Hyung Gu Park ,  Hong Jin Kim ,  Yoo Hwan Kim ,  Dong Su Lee

    IPC分类号： H03M1/12 ,  H03M1/06

    CPC分类号： H03M1/06 ,  H03M1/502

    摘要： There are provided an analog-to-digital signal conversion method and apparatus therefor, and a digital phase locked loop circuit including the same. The analog-to-digital signal conversion method may include: generating a first digital output signal having N number of bits by comparing each of N number of delay signals detected from output terminals of N number of delay cells with a reference signal; generating a second digital output signal by comparing an auxiliary delay signal generated by an (N+1)th delay cell with the reference signal; and determining a change in a delay time of each of the N number of delay cells based on the first digital output signal and the second digital output signal.

    摘要翻译： 提供了一种模拟 - 数字信号转换方法及其装置，以及包括该数字锁相环电路的数字锁相环电路。 模数信号转换方法可以包括：通过将从N个延迟单元的输出端子检测的N个延迟信号中的每一个与参考信号相比较来产生具有N个比特数的第一数字输出信号; 通过将由第（N + 1）个延迟单元产生的辅助延迟信号与参考信号进行比较来产生第二数字输出信号; 以及基于所述第一数字输出信号和所述第二数字输出信号确定所述N个延迟单元中的每一个的延迟时间的变化。

    Analog-to-digital signal conversion method and apparatus therefor
    9.
    发明授权
    Analog-to-digital signal conversion method and apparatus therefor 失效
    模数信号转换方法及其装置

    公开(公告)号：US08618972B1

    公开(公告)日：2013-12-31

    申请号：US13620352

    申请日：2012-09-14

    申请人： Yoo Sam Na ,  Kang Yoon Lee ,  Young Gun Pu ,  Hyung Gu Park ,  Hong Jin Kim ,  Yoo Hwan Kim ,  Dong Su Lee

    发明人： Yoo Sam Na ,  Kang Yoon Lee ,  Young Gun Pu ,  Hyung Gu Park ,  Hong Jin Kim ,  Yoo Hwan Kim ,  Dong Su Lee

    IPC分类号： H03M1/12

    CPC分类号： H03M1/06 ,  H03M1/502

    摘要： There are provided an analog-to-digital signal conversion method and apparatus therefor, and a digital phase locked loop circuit including the same. The analog-to-digital signal conversion method may include: generating a first digital output signal having N number of bits by comparing each of N number of delay signals detected from output terminals of N number of delay cells with a reference signal; generating a second digital output signal by comparing an auxiliary delay signal generated by an (N+1)th delay cell with the reference signal; and determining a change in a delay time of each of the N number of delay cells based on the first digital output signal and the second digital output signal.

    摘要翻译： 提供了一种模拟 - 数字信号转换方法及其装置，以及包括该数字锁相环电路的数字锁相环电路。 模数信号转换方法可以包括：通过将从N个延迟单元的输出端子检测的N个延迟信号中的每一个与参考信号相比较来产生具有N个比特数的第一数字输出信号; 通过将由第（N + 1）个延迟单元产生的辅助延迟信号与参考信号进行比较来产生第二数字输出信号; 以及基于所述第一数字输出信号和所述第二数字输出信号确定所述N个延迟单元中的每一个的延迟时间的变化。