-
公开(公告)号：US06320421B1
公开(公告)日：2001-11-20
申请号：US09583720
申请日：2000-05-30
申请人： Yohei Akita , Naoki Kato , Kazuo Yano
发明人： Yohei Akita , Naoki Kato , Kazuo Yano
IPC分类号： H03K19094
CPC分类号： H03K3/356156 , H03K3/35625 , H03K17/693
摘要： There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function. A logic circuit having the circuitry shown in FIG. 6 will be described briefly. Two transmission gates TG10a (TG10b) and TG11 and two inverters IV10 and IV11 are used to define a data propagation path from an input port I1 (I2) to an output port O1. Thus, four logic gates are located along the path in the same manner as they are in a conventional D flip-flop circuit. The transmission gate TG10a (TG10b) is controlled using a NOR circuit 12a that inputs a clock CLK and a select signal /sel that is the reverse of a select signal sel (NOR circuit 12b that inputs the clock CLK and the select signal sel). The transmission gate TG11 is controlled with the clock CLK. Either of two input data items is selected based on the select signals, and then output. When a D flip-flop circuit with a data-selecting function that causes the same delay time as a conventional D flip-flop circuit is adapted to a pipeline circuit, the action of the pipeline circuit can be speeded up.
摘要翻译： 提供了与常规逻辑电路相同的延迟时间并用作具有数据选择功能的D触发器电路的逻辑电路。 将简要描述图6。 两个传输门TG10a（TG10b）和TG11以及两个反相器IV10和IV11用于定义从输入端口I1（I2）到输出端口O1的数据传播路径。 因此，沿着路径以与常规D触发器电路中相同的方式定位四个逻辑门。 传输门TG10a（TG10b）使用NOR电路12a进行控制，NOR电路12a输入时钟CLK和与选择信号sel相反的选择信号/ sel（输入时钟CLK和选择信号sel的NOR电路12b）。 传输门TG11由时钟CLK控制。 基于选择信号选择两个输入数据项之一，然后输出。当具有导致与常规D触发器电路相同的延迟时间的数据选择功能的D触发器电路适用于管道 电路，流水线电路的动作可以加快。
-
公开(公告)号：US06970017B2
公开(公告)日：2005-11-29
申请号：US09946440
申请日：2001-09-06
申请人： Yohei Akita , Naoki Kato , Kazuo Yano
发明人： Yohei Akita , Naoki Kato , Kazuo Yano
IPC分类号： H03K3/356 , H03K3/3562 , H03K17/693 , H03K19/094
CPC分类号： H03K3/356156 , H03K3/35625 , H03K17/693
摘要： There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function.A logic circuit having the circuitry shown in FIG. 6 will be described briefly. Two transmission gates TG10a (TG10b) and TG11 and two inverters IV10 and IV11 are used to define a data propagation path from an input port I1 (I2) to an output port O1. Thus, four logic gates are located along the path in the same manner as they are in a conventional D flip-flop circuit. The transmission gate TG10a (TG10b) is controlled using a NOR circuit 12a that inputs a clock CLK and a select signal /sel that is the reverse of a select signal sel (NOR circuit 12b that inputs the clock CLK and the select signal sel). The transmission gate TG11 is controlled with the clock CLK. Either of two input data items is selected based on the select signals, and then output.When a D flip-flop circuit with a data-selecting function that causes the same delay time as a conventional D flip-flop circuit is adapted to a pipeline circuit, the action of the pipeline circuit can be speeded up.
摘要翻译： 提供了与常规逻辑电路相同的延迟时间并用作具有数据选择功能的D触发器电路的逻辑电路。 具有图1所示电路的逻辑电路。 将简要描述图6。 使用两个传输门TG10a（TG10b）和TG11以及两个反相器IV10和IV11来定义从输入端口I 1（I 2）到输出端口O 1的数据传播路径。 因此，沿着路径以与常规D触发器电路中相同的方式定位四个逻辑门。 传输门TG10a（TG10b）使用输入时钟CLK和与选择信号sel相反的选择信号/ sel（输入时钟CLK的NOR电路12b）的NOR电路12a和 选择信号sel）。 传输门TG11由时钟CLK控制。 基于选择信号选择两个输入数据项之一，然后输出。 当具有导致与常规D触发器电路相同的延迟时间的数据选择功能的D触发器电路适用于流水线电路时，可以加速流水线电路的动作。
-
3.发明授权Semiconductor integrated circuit device, recording medium stored with cell library, and method for designing semiconductor integrated circuit 有权半导体集成电路器件，存储有单元库的记录介质和用于设计半导体集成电路的方法公开(公告)号：US06380764B1
公开(公告)日：2002-04-30
申请号：US09582327
申请日：2000-06-23
申请人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
发明人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
IPC分类号： H03K1900
CPC分类号： H03K19/1731 , G06F17/505 , H03K19/0013
摘要： Disclosed is a semiconductor integrated circuit device constructed of MOSFETs in which there is attained a harmony between increase in consumption power due to a leakage current and operating speed of the MOSFETs in a suitable manner, and among a plurality of signal paths in the semiconductor integrated circuit device, a path which has a margin in delay is constructed with MOSFETs each with a high threshold voltage, while a path which has no margin in delay is constructed with MOSFETs each with a low threshold voltage which has a large leakage current but a high operating speed, in light of a delay with which a signal is transmitted along a signal path.
摘要翻译： 公开了一种由MOSFET构成的半导体集成电路器件，其中以适当的方式在MOSFET的漏电流和操作速度增加的消耗功率增加之间以及半导体集成电路中的多个信号路径之间达到和谐 器件，具有延迟裕度的路径由具有高阈值电压的MOSFET构成，而不具有延迟裕度的路径由具有低阈值电压的MOSFET构成，其具有大的漏电流但操作性高 根据信号沿着信号路径发送的延迟。
-
4.发明授权Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit 有权半导体集成电路器件，其上存储有单元库的存储介质和用于半导体集成电路的设计方法公开(公告)号：US07129741B2
公开(公告)日：2006-10-31
申请号：US10827291
申请日：2004-04-20
申请人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
发明人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
IPC分类号： H03K19/23
CPC分类号： H03K19/1731 , G06F17/505 , H03K19/0013
摘要： This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.
摘要翻译： 本发明提供了一种存储介质，其上存储有一个单元库以设计半导体集成电路以满足低功耗和高速操作，以及使用该单元库的设计方法。 细胞库与具有相同功能和相同形状的延迟和功耗不同的至少两种细胞登记。 为了满足半导体集成电路的规格，从单元库的至少两种单元中选择一个单元。
-
5.发明授权Semiconductor integrated circuit device, storage medium on which cell library is stored and designing method for semiconductor integrated circuit 有权半导体集成电路器件，其上存储有单元库的存储介质和用于半导体集成电路的设计方法公开(公告)号：US06769110B2
公开(公告)日：2004-07-27
申请号：US10084435
申请日：2002-02-28
申请人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
发明人： Naoki Katoh , Kazuo Yano , Yohei Akita , Mitsuru Hiraki
IPC分类号： G06F1750
CPC分类号： H03K19/1731 , G06F17/505 , H03K19/0013
摘要： This invention provides a storage medium on which there is stored a cell library to design a semiconductor integrated circuit to satisfy low power consumption and high speed operation and a design method using the cell library. The cell library is registered with at least two kinds of cells which are different in delay and power consumption while having the same function and the same shape. To satisfy the specification of the semiconductor integrated circuit, one cell is selected from at least two kinds of cells of the cell library.
摘要翻译： 本发明提供了一种存储介质，其上存储有一个单元库以设计半导体集成电路以满足低功耗和高速操作，以及使用该单元库的设计方法。 细胞库与具有相同功能和相同形状的延迟和功耗不同的至少两种细胞登记。 为了满足半导体集成电路的规格，从单元库的至少两种单元中选择一个单元。
-
公开(公告)号：US20090282213A1
公开(公告)日：2009-11-12
申请号：US12505128
申请日：2009-07-17
CPC分类号： H03K19/17752 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.
摘要翻译： 能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。 该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径 切换OSW。 包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持 从多个数据输入节点中的任何一个输入的数据。
-
7.发明授权Semiconductor integrated circuit including multiple basic cells formed in arrays 失效半导体集成电路包括以阵列形成的多个基本单元公开(公告)号：US07568084B2
公开(公告)日：2009-07-28
申请号：US10886616
申请日：2004-07-09
IPC分类号： G06F15/00
CPC分类号： H03K19/17752 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.
摘要翻译： 能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。 该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径 切换OSW。 包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持 从多个数据输入节点中的任何一个输入的数据。
-
公开(公告)号：US20050015572A1
公开(公告)日：2005-01-20
申请号：US10886616
申请日：2004-07-09
IPC分类号： H01L21/82 , G06F15/80 , H03K19/177 , G06F15/00
CPC分类号： H03K19/17752 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFF0 between the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.
摘要翻译： 能够具有固定工作频率的基本单元能够动态地改变配置信息，而与能够有效地利用LSI半导体集成电路中的单元内的算术逻辑电路的配置信息无关。 该电路具有连接到多个数据输入节点的输入开关ISW，连接到多个数据输出节点的输出开关OSW，在输入开关ISW和输出端之间包含算术逻辑电路ALU和结果存储触发器CFF0的第一数据路径 切换OSW。 包含输入开关ISW和输出开关OSW之间的数据传输触发器的第二数据路径，结果存储触发器CFF存储来自算术逻辑电路ALU的计算结果数据，并且数据传送触发器保持 从多个数据输入节点中的任何一个输入的数据。
-
公开(公告)号：US07039576B2
公开(公告)日：2006-05-02
申请号：US09987317
申请日：2001-11-14
申请人： Yohei Akita
发明人： Yohei Akita
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/66
摘要： A system designed, including commercially distributed modules protected as intellectual property (IP), is verified in a manner that the IP provider and the user communicate with each other over a communication line to complete the system design verification. A system verification equipment to be operated by the IP provider receives from the system designer across the communication line an input vector at time n to a module provided to the system designer who designed the system integrated using one or more provided IP modules. After simulating the module operation with the input vector, the verification equipment returns an output vector obtained at time n+1 to the system designer over the communication line. The verification equipment examines the input vectors to the provided IP modules and records statistics information thereof, based on which the provider will quantitatively understand how the provided modules have been used. Such information is used by the provider to determine the specifications of modules to be provided next time and to market modules meeting user needs. The verification equipment determines the service charge for each IP user by the quantity of load worked on its verification system to fulfill the service, according to the quantity of input vector data transmitted to the equipment by the user. Furthermore, the verification equipment encrypts vector data before transmitting it across the communication line and decrypts vector data after receiving it over the line such that the data is prevented from intercepted by a third party.
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.022 秒)
