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公开(公告)号：US20050086621A1
公开(公告)日：2005-04-21
申请号：US10895821
申请日：2004-07-22
CPC分类号： G06F17/5045
摘要： A circuit from which a buffer and an inverter are removed without changing logic is displayed. Such a circuit is obtained by a first or a second method. With the first method, all buffers which do not change logic and, when a clock path is divided at a branch point of wiring, all pairs of inverters located on each divided clock path are removed from the clock circuit. With the second method, a logic element located on a plurality of clock paths is copied and added to the clock circuit, all buffers which do not change logic and all pairs of inverters located between logic elements other than the above buffers are removed, and redundant partial circuits, if any, realizing the same logic and being located on a plurality of clock paths are removed. Thus, the clock circuit can be displayed so as to facilitate a designer's understanding of logic.
摘要翻译： 显示缓冲器和逆变器在不改变逻辑的情况下被去除的电路。 这种电路是通过第一种或第二种方法获得的。 利用第一种方法，不改变逻辑的所有缓冲器，并且当在布线的分支点处划分时钟路径时，位于每个划分时钟路径上的所有反相器对都从时钟电路中去除。 利用第二种方法，将位于多个时钟路径上的逻辑元件复制并添加到时钟电路中，除去不改变逻辑的所有缓冲器和位于除了上述缓冲器之外的逻辑元件之间的所有反相器对，并且冗余 去除实现相同逻辑并位于多个时钟路径上的部分电路（如果有的话）。 因此，可以显示时钟电路，以便于设计者对逻辑的理解。
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公开(公告)号：US20050060676A1
公开(公告)日：2005-03-17
申请号：US10817959
申请日：2004-04-06
CPC分类号： G06F17/5031 , G06F1/10 , G06F17/5045 , G06F17/5059 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.
摘要翻译： 本发明提供一种半导体集成电路，其中即使存在制造变异性，也不可能发生定时误差。 分别包括在第一和第二时钟电路11和12中的逻辑单元16和17由均匀尺寸的晶体管形成。 即使存在制造变化，第一时钟电路11的延迟时间t1和第二时钟电路12的延迟时间t2增加或减少相同的时间量。 因此，在第二触发器15中不可能发生定时误差。每个时钟单元中包括的逻辑单元可以由具有均匀矩形扩散区域的晶体管形成。
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公开(公告)号：US20060253823A1
公开(公告)日：2006-11-09
申请号：US11482852
申请日：2006-07-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F1/10 , G06F17/5045 , G06F17/5059 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.
摘要翻译： 本发明提供一种半导体集成电路，其中即使存在制造变异性，也不可能发生定时误差。 分别包括在第一和第二时钟电路11和12中的逻辑单元16和17由均匀尺寸的晶体管形成。 即使存在制造变化，第二时钟电路11的延迟时间t 1> 1和第二时钟电路12的延迟时间t 2> 2>增加或减少相同的量 的时间。 因此，在第二触发器15中不可能发生定时误差。每个时钟单元中包括的逻辑单元可以由具有均匀矩形扩散区域的晶体管形成。
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公开(公告)号：US20060253822A1
公开(公告)日：2006-11-09
申请号：US11482851
申请日：2006-07-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F1/10 , G06F17/5045 , G06F17/5059 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.
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公开(公告)号：US07334210B2
公开(公告)日：2008-02-19
申请号：US10980269
申请日：2004-11-04
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/11807
摘要： In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.
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公开(公告)号：US20050097492A1
公开(公告)日：2005-05-05
申请号：US10980269
申请日：2004-11-04
IPC分类号： G06F17/50 , G06F9/45 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118
CPC分类号： G06F17/5068 , H01L27/11807
摘要： In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.
摘要翻译： 在半导体集成电路中，由于电源线中包含电阻成分，所以提供给时钟路径上的单元的电源电压下降，造成时钟偏移。 为了避免这个问题，以时钟路径上的单元10为中心设置单元放置禁止区域，在该单元放置禁止区域中不设置用于执行逻辑运算的单元。 此外，可以为由紧密放置在一起的多个单元形成的每个单元组设置单元布置禁止区域。 此外，可以将电容单元放置在电池放置禁止区域中。
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公开(公告)号：US09710146B2
公开(公告)日：2017-07-18
申请号：US14241520
申请日：2012-08-07
申请人： Tatsuya Tokunaga , Hiroki Taniguchi
发明人： Tatsuya Tokunaga , Hiroki Taniguchi
IPC分类号： G06F3/0485 , G09G5/34 , A61B6/00 , G09G5/377 , A61B5/00
CPC分类号： G06F3/04855 , A61B5/742 , A61B5/7435 , A61B6/465 , G06F3/0485 , G06F2203/04806 , G09G5/34 , G09G5/377 , G09G2380/08
摘要： Provided is a technology that supports a user in easily selecting an image of interest from among a large quantity of continuous images while making the best use of characteristics of a scroll function. The technology prepares a first scroll area that receives an indication for sequentially scrolling images to be displayed on a display screen among the large quantity of continuous images by a predetermined first amount of a scroll; and a second scroll area that receives an indication for sequentially scrolling the images by the amount of a scroll smaller than the first amount of a scroll, in a case where the number of the continuous images is greater than the maximum number of designatable positions of the first scroll area.
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公开(公告)号：US08597458B2
公开(公告)日：2013-12-03
申请号：US13258977
申请日：2010-02-18
申请人： Hiroki Taniguchi , Masashi Hosokawa , Akane Sakai
发明人： Hiroki Taniguchi , Masashi Hosokawa , Akane Sakai
IPC分类号： B29C41/36 , B29C41/50 , A61F13/535
CPC分类号： A61F13/15658
摘要： A manufacturing method for a composite sheet which includes: conveying a first continuous sheet in a first direction so as to abut a depressed surface of a mold member; forming an absorbent body by depositing liquid-absorbent particles on a portion of the first sheet proximal to a suction hole of the mold; and joining a second sheet over the first sheet having the absorbent body that is deposited therebetween, the second sheet being continuously transported in the first direction. A plurality of opposed slope members guide the liquid-absorbent particles onto the first sheet located on the mold member. At least one of the plurality of slope members causes the liquid-absorbent particles to reverse their falling direction from an upper slope member.
摘要翻译： 一种复合片材的制造方法，其特征在于，包括：沿第一方向输送第一连续片材，以抵靠模具部件的凹陷面; 通过在靠近所述模具的吸入孔的所述第一片材的一部分上沉积吸收液体的颗粒来形成吸收体; 并且在第一片材上接合第二片材，所述第一片材具有沉积在其间的吸收体，所述第二片材沿所述第一方向连续传输。 多个相对的斜面构件将吸液性颗粒引导到位于模具构件上的第一片上。 多个倾斜部件中的至少一个使吸液性粒子从上斜面部件反转其下降方向。
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公开(公告)号：US20110079914A1
公开(公告)日：2011-04-07
申请号：US12947344
申请日：2010-11-16
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译： 本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。 在标准单元中，第一信号线在第一方向上延伸。 第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。 第二和第三信号线的宽度大于第一信号线的宽度。
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公开(公告)号：US6139785A
公开(公告)日：2000-10-31
申请号：US273054
申请日：1999-03-19
CPC分类号： C08J3/095 , C08J5/18 , C08L1/10 , C08L1/12 , C08J2301/10
摘要： The present invention provides a cellulose ester composition, containing 1 to 99% by weight of cellulose triacetate prepared by substituting hydroxyl groups of cellulose with acetyl and having a degree of substitution with acetyl, DSace, which satisfies the relationship: 2.7.ltoreq.DSace.ltoreq.3.0, and 99 to 1% by weight of a mixed fatty acid ester of cellulose prepared by substituting hydroxyl groups of cellulose with acetyl and acyl groups having three or more carbon atoms and having degrees of substitution with acetyl and acyl groups having three or more carbon atoms, DSace and DSacyl, respectively, which satisfy the relationships: (I) 2.20.ltoreq.DSace.ltoreq.2.95, (II) 0.05.ltoreq.DSacyl.ltoreq.0.80 and (III) 2.60.ltoreq.DSace+DSacyl.ltoreq.3.00.
摘要翻译： 本发明提供一种纤维素酯组合物，其含有1至99重量％的纤维素三乙酸酯，其通过用乙酰基取代纤维素的羟基并且具有乙酰基取代度DSace制备，其满足以下关系：2.7 < / = 3.0和99〜1重量％的纤维素的混合脂肪酸酯，其通过用具有三个或更多个碳原子的乙酰基和酰基取代纤维素的羟基并且具有三个或更多个乙酰基和酰基的取代度而制备 分别满足以下关系的更多的碳原子，DSace和DSacyl：（I）2.20
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