公开(公告)号：US20100291762A1

公开(公告)日：2010-11-18

申请号：US12627403

申请日：2009-11-30

申请人： Yoichiro TARUI

发明人： Yoichiro TARUI

IPC分类号： H01L21/265

CPC分类号： H01L29/872 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process.

摘要翻译： 提供了一种制造碳化硅半导体器件的方法，其包括以下步骤：在第一导电类型的碳化硅晶片的表面上形成第二导电类型的第一区域，其具有通过离子注入铝作为第一杂质而具有其内部的预定空间 和硼作为第二杂质; 通过激活退火处理将从第一区域注入的硼离子扩散到其相邻区域，从第一区域在碳化硅晶片的表面形成JTE区域的步骤; 在第一区域内的空间和第一区域的内部在碳化硅晶片的表面上形成第一电极的步骤; 以及在所述碳化硅晶片的相对表面上形成第二电极的步骤。 因此，可以形成具有宽范围的杂质浓度和期望的击穿电压的JTE区域，而不增加制造工艺的步骤数量。

公开(公告)号：US20110223694A1

公开(公告)日：2011-09-15

申请号：US12961868

申请日：2010-12-07

申请人： Yukio UDA ,  Koichi SEKIYA ,  Kazuo KOBAYASHI ,  Yoichiro TARUI

发明人： Yukio UDA ,  Koichi SEKIYA ,  Kazuo KOBAYASHI ,  Yoichiro TARUI

IPC分类号： H01L21/66

CPC分类号： H01L29/7802 ,  C23C16/325 ,  C23C16/56 ,  H01L21/046 ,  H01L22/12 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068 ,  Y10S438/931

摘要： A wafer WF is mounted in a substrate holder, and the substrate holder is placed in a film forming furnace. The film forming furnace is evacuated by a vacuum pump through a gas discharge part to remove remaining oxygen as completely as possible. Then, a temperature in the film forming furnace is heated to a range of 800° C. to 950° C. under reduced pressure while an inert gas such as Ar or helium (He) is being introduced through a gas introduction part. When the temperature reaches this temperature range, an inflow of the inert gas is stopped. Vaporized ethanol is introduced as a source gas into the film forming furnace through the gas introduction part, thus forming a graphite film on an entire surface of the wafer WF.

摘要翻译： 将晶片WF安装在基板保持器中，并将基板保持器放置在成膜炉中。 成膜炉通过真空泵通过气体排出部分排出，以尽可能完全地除去剩余的氧气。 然后，将成膜炉中的温度在减压下加热至800℃至950℃的范围，同时通过气体引入部分引入诸如Ar或氦（He）的惰性气体。 当温度达到该温度范围时，停止惰性气体的流入。 通过气体导入部将蒸发的乙醇作为原料气体引入成膜炉，从而在晶片WF的整个表面上形成石墨膜。

公开(公告)号：US20100258815A1

公开(公告)日：2010-10-14

申请号：US12621963

申请日：2009-11-19

申请人： Yoichiro TARUI

发明人： Yoichiro TARUI

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L21/0455 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/66068

摘要： An objective is to provide a manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the manufacturing method increase of the manufacturing cost can also be prevented as much as possible. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch

摘要翻译： 目的是提供一种碳化硅半导体器件的制造方法，其中施加到栅极氧化膜的电场可以被放宽，从而可以确保可靠性，并且通过制造方法也可以防止制造成本的增加，因为 尽可能的 形成阱区域，沟道区域和栅电极，使得相对于源极区域的内侧的阱区域，沟道区域和栅极电极的延伸长度为Lwell，Lch和 Lg分别满足Lch

公开(公告)号：US20120112266A1

公开(公告)日：2012-05-10

申请号：US13197237

申请日：2011-08-03

申请人： Yoichiro TARUI

发明人： Yoichiro TARUI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L23/544 ,  H01L29/0657 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66068 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of the present invention includes: a semiconductor substrate of a first conductive type; an epitaxial layer of the first conductive type formed on the semiconductor substrate and having a protrusion formed on a surface thereof; a well region of a second conductive type formed on the surface of the epitaxial layer at each side of the protrusion; a source region of the first conductive type selectively formed in a surface of the well region; a gate insulating film formed so as to cover at least the protrusion and the surface of the well region; and a gate electrode formed on a part of the gate insulating film corresponding to the protrusion. The gate insulating film is thicker in a region thereof corresponding to an upper surface of the protrusion than the other regions thereof.

摘要翻译： 本发明的半导体器件包括：第一导电类型的半导体衬底; 所述第一导电类型的外延层形成在所述半导体衬底上并且在其表面上形成有突起; 形成在所述突起的每一侧的所述外延层的表面上的第二导电类型的阱区; 所述第一导电类型的源极区选择性地形成在所述阱区的表面中; 形成为至少覆盖所述阱区域的突起和表面的栅极绝缘膜; 以及形成在与所述突起相对应的所述栅极绝缘膜的一部分上的栅电极。 栅极绝缘膜在与突起的上表面相对应的区域中比其他区域更厚。

公开(公告)号：US20110244643A1

公开(公告)日：2011-10-06

申请号：US13164430

申请日：2011-06-20

申请人： Yoichiro TARUI

发明人： Yoichiro TARUI

IPC分类号： H01L21/336

CPC分类号： H01L21/0455 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/66068

摘要： A manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the method manufacturing costs can be reduced. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch

摘要翻译： 可以缓和施加到栅极氧化膜的电场的碳化硅半导体器件的制造方法，从而可以确保可靠性，并且通过该方法可以降低制造成本。 形成阱区域，沟道区域和栅电极，使得相对于源极区域的内侧的阱区域，沟道区域和栅极电极的延伸长度为Lwell，Lch和 Lg分别满足Lch

公开(公告)号：US20110095301A1

公开(公告)日：2011-04-28

申请号：US12820480

申请日：2010-06-22

申请人： Yoichiro TARUI

发明人： Yoichiro TARUI

IPC分类号： H01L29/24 ,  H01L29/47

CPC分类号： H01L29/872 ,  H01L23/544 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66143 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： There was a problem that it was difficult to manufacture silicon carbide semiconductor devices with suppressed variations in characteristics without increasing the number of process steps. A silicon carbide semiconductor device according to the present invention includes an N type SiC substrate and an N type SiC epitaxial layer as a silicon carbide semiconductor substrate of a first conductivity type, a plurality of recesses intermittently formed in a surface of the N type SiC epitaxial layer, P type regions as second-conductivity-type semiconductor layers formed in the N type SiC epitaxial layer in the bottoms of the plurality of recesses, and a Schottky electrode selectively formed over the surface of the N type SiC epitaxial layer, wherein the plurality of recesses all have an equal depth.

摘要翻译： 存在难以制造具有抑制的特性变化的碳化硅半导体器件而不增加工艺步骤数量的问题。 根据本发明的碳化硅半导体器件包括N型SiC衬底和作为第一导电类型的碳化硅半导体衬底的N型SiC外延层，在N型SiC外延表面间断地形成的多个凹槽 形成在多个凹部的底部的N型SiC外延层中的作为第二导电型半导体层的P型区域，以及选择性地形成在N型SiC外延层的表面上的肖特基电极，其中， 的凹槽都具有相同的深度。

公开(公告)号：US20100289110A1

公开(公告)日：2010-11-18

申请号：US12650957

申请日：2009-12-31

申请人： Yoichiro TARUI ,  Atsushi Narazaki ,  Ryoichi Fujii

发明人： Yoichiro TARUI ,  Atsushi Narazaki ,  Ryoichi Fujii

IPC分类号： H01L23/58

CPC分类号： H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/408 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device using one or more guard rings includes a p-type guard ring region surrounding a pn junction region, an insulating film covering the p-type guard ring region, one or more conductive films electrically connected with the p-type guard ring region through one or more contact holes made in the insulating film, and a semi-insulating film covering the insulating film and the conductive films. Thus, a desired breakdown voltage characteristic can be ensured even if a foreign matter or the like adheres to a surface of the conductive films.

摘要翻译： 使用一个或多个保护环的半导体器件包括围绕pn结区域的p型保护环区域，覆盖p型保护环区域的绝缘膜，与p型保护环区域电连接的一个或多个导电膜 通过在绝缘膜中形成的一个或多个接触孔，以及覆盖绝缘膜和导电膜的半绝缘膜。 因此，即使异物等附着在导电膜的表面，也能够确保期望的击穿电压特性。

公开(公告)号：US20120132924A1

公开(公告)日：2012-05-31

申请号：US13252565

申请日：2011-10-04

申请人： Yoichiro TARUI ,  Naoto Kaguchi ,  Takuyo Nakamura

发明人： Yoichiro TARUI ,  Naoto Kaguchi ,  Takuyo Nakamura

IPC分类号： H01L29/161

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7811

摘要： In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 μm from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.

摘要翻译： 在具有终止区域为JTE区域或FLR的碳化硅半导体器件的制造中，用于去除形成在端接区域的表面中的损伤层的蚀刻量的边界被扩大。 碳化硅半导体器件具有在半导体元件的端部处的JTE（结终端延伸）区域或FLR（场限制环）的端接区域。 终端区域由离子注入的一个步骤形成，其中杂质的种类和植入能量被固定。 在终端区域的深度方向的杂质浓度分布中，最浅位置的浓度峰位于比表面0.35μm以上的位置，表面部分的浓度不超过最浅的位置的十分之一 浓度峰值。

公开(公告)号：US20110147766A1

公开(公告)日：2011-06-23

申请号：US13037043

申请日：2011-02-28

申请人： Yoichiro TARUI

发明人： Yoichiro TARUI

IPC分类号： H01L29/161

CPC分类号： H01L29/872 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process.

摘要翻译： 提供了一种制造碳化硅半导体器件的方法，其包括以下步骤：在第一导电类型的碳化硅晶片的表面上形成第二导电类型的第一区域，其具有通过离子注入铝作为第一杂质而具有其内部的预定空间 和硼作为第二杂质; 通过激活退火处理将从第一区域注入的硼离子扩散到其相邻区域，从第一区域在碳化硅晶片的表面形成JTE区域的步骤; 在第一区域内的空间和第一区域的内部在碳化硅晶片的表面上形成第一电极的步骤; 以及在所述碳化硅晶片的相对表面上形成第二电极的步骤。 因此，可以形成具有宽范围的杂质浓度和期望的击穿电压的JTE区域，而不增加制造工艺的步骤数量。