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    Erasing method in non-volatile memory device
    3.
    发明授权
    Erasing method in non-volatile memory device 有权
    非易失性存储器件中的擦除方法

    公开(公告)号：US06724661B2

    公开(公告)日：2004-04-20

    申请号：US10090902

    申请日：2002-05-31

    申请人： Yong-Kyu Lee ,  Dong-Jun Kim ,  Min-Soo Cho ,  Eui-Youl Ryu ,  Jin-Ho Kim

    发明人： Yong-Kyu Lee ,  Dong-Jun Kim ,  Min-Soo Cho ,  Eui-Youl Ryu ,  Jin-Ho Kim

    IPC分类号： G11C1604

    CPC分类号： G11C16/14

    摘要： A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.

    摘要翻译： 一种在存储单元中执行擦除操作的方法。 分别在源极和漏极区域施加第一电压和第二电压达预定的擦除时间; 并且第一和第二电压在源极和漏极区之间彼此切换至少一次以用于擦除时间。 因此，孔容易地注入到源极和漏极区域以及沟道横向表面，并且存储均匀且高速的擦除操作。

    Nonvolatile memory cells having split gate structure and methods of fabricating the same
    5.
    发明申请
    Nonvolatile memory cells having split gate structure and methods of fabricating the same 有权

    公开(公告)号：US20050056880A1

    公开(公告)日：2005-03-17

    申请号：US10981115

    申请日：2004-11-04

    申请人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    发明人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    IPC分类号： G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L29/76

    CPC分类号： H01L27/11556 ,  H01L27/115

    摘要： Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

    Nonvolatile memory cells having split gate structure and methods of fabricating the same
    6.
    发明授权
    Nonvolatile memory cells having split gate structure and methods of fabricating the same 有权
    具有分裂栅极结构的非易失性存储单元及其制造方法

    公开(公告)号：US07180124B2

    公开(公告)日：2007-02-20

    申请号：US10981115

    申请日：2004-11-04

    申请人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    发明人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11556 ,  H01L27/115

    摘要： Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

    摘要翻译： 提供具有分裂栅极结构的非易失性存储单元及其制造方法。 非易失性存储单元包括限定在半导体衬底的预定区域的有源区。 每个有源区的一部分被蚀刻以形成单元沟槽区。 绝缘浮动栅极设置在与穿过有源区域的方向平行的一对侧壁上。 源区域设置在单元沟槽区域的底表面处。 浮置栅极之间的间隙区填充有与源极区域电连接的公共源极线。 公共源极线沿着与有源区域交叉的方向延伸。 与浮动栅极相邻的有源区域被与公共源极线平行的字线覆盖。 漏极区域设置在与字线相邻的有源区域中。 漏极区域电连接到跨越字线的位线。

    Nonvolatile memory cells having split gate structure and methods of fabricating the same
    7.
    发明授权
    Nonvolatile memory cells having split gate structure and methods of fabricating the same 有权

    公开(公告)号：US07183154B2

    公开(公告)日：2007-02-27

    申请号：US10980992

    申请日：2004-11-04

    申请人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    发明人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11556 ,  H01L27/115

    摘要： Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

    Method of forming flash memory
    8.
    发明授权
    Method of forming flash memory 失效
    形成闪存的方法

    公开(公告)号：US06730565B2

    公开(公告)日：2004-05-04

    申请号：US10277848

    申请日：2002-10-22

    申请人： Min-Soo Cho ,  Dong-Jun Kim ,  Jin-Woo Kim

    发明人： Min-Soo Cho ,  Dong-Jun Kim ,  Jin-Woo Kim

    IPC分类号： H10L21336

    CPC分类号： H01L27/11519 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521

    摘要： The present invention provides a method of forming a split gate type flash memory. After exposure of a floating gate layer between silicon nitride layers, a conductive layer spacer is formed on a sidewall of the silicon nitride layer pattern. The conductive layer spacer is formed in a floating gate of a later-completed flash memory to form a tip on which tunneling is centralized in an erase operation. That is, the spacer is formed on a sidewall of the silicon nitride layer pattern over the floating gate layer to form the tunneling tip.

    摘要翻译： 本发明提供一种形成分离式闪存的方法。 在氮化硅层之间的浮栅层暴露之后，在氮化硅层图案的侧壁上形成导电层间隔物。 导电层隔离物形成在随后完成的闪速存储器的浮动栅极中，以形成在擦除操作中将隧道集中在其上的尖端。 也就是说，间隔物形成在浮动栅极层上的氮化硅层图案的侧壁上以形成隧道末端。

    Nonvolatile memory cells having split gate structure and methods of fabricating the same
    9.
    发明申请
    Nonvolatile memory cells having split gate structure and methods of fabricating the same 有权

    公开(公告)号：US20050064655A1

    公开(公告)日：2005-03-24

    申请号：US10980992

    申请日：2004-11-04

    申请人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    发明人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    IPC分类号： G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238

    CPC分类号： H01L27/11556 ,  H01L27/115

    摘要： Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

    Nonvolatile memory cells having split gate structure and methods of fabricating the same
    10.
    发明授权
    Nonvolatile memory cells having split gate structure and methods of fabricating the same 失效
    具有分裂栅极结构的非易失性存储单元及其制造方法

    公开(公告)号：US06867082B2

    公开(公告)日：2005-03-15

    申请号：US10844240

    申请日：2004-05-12

    申请人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    发明人： Jin-Woo Kim ,  Dong-Jun Kim ,  Min-Soo Cho ,  Dai-Geun Kim

    IPC分类号： G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238

    CPC分类号： H01L27/11556 ,  H01L27/115

    摘要： Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

    摘要翻译： 提供具有分裂栅极结构的非易失性存储单元及其制造方法。 非易失性存储单元包括限定在半导体衬底的预定区域的有源区。 每个有源区的一部分被蚀刻以形成单元沟槽区。 绝缘浮动栅极设置在与穿过有源区域的方向平行的一对侧壁上。 源区域设置在单元沟槽区域的底表面处。 浮置栅极之间的间隙区填充有与源极区域电连接的公共源极线。 公共源极线沿着与有源区域交叉的方向延伸。 与浮动栅极相邻的有源区域被与公共源极线平行的字线覆盖。 漏极区域设置在与字线相邻的有源区域中。 漏极区域电连接到跨越字线的位线。