Sense amplifiers including bipolar transistor input buffers and field
effect transistor latch circuits
    1.
    发明授权
    Sense amplifiers including bipolar transistor input buffers and field effect transistor latch circuits 失效
    感应放大器包括双极晶体管输入缓冲器和场效应晶体管锁存电路

    公开(公告)号:US5894233A

    公开(公告)日:1999-04-13

    申请号:US965562

    申请日:1997-11-06

    Applicant: Yong-jin Yoon

    Inventor: Yong-jin Yoon

    CPC classification number: G11C7/062

    Abstract: Sense amplifiers for integrated circuit memory devices including a bipolar transistor voltage gain input buffer and a first effect transistor latch circuit. The bipolar transistor voltage gain input buffer is responsive to a pair of complementary input signals from a memory cell, to amplify the voltage differential between the pair of complementary input signals. The field effect transistor latch circuit is responsive to the bipolar transistor voltage gain input buffer, to latch the voltage differential so amplified, and thereby produce a pair of complementary output signals.

    Abstract translation: 用于集成电路存储器件的感测放大器,包括双极晶体管电压增益输入缓冲器和第一效应晶体管锁存电路。 双极晶体管电压增益输入缓冲器响应来自存储单元的一对互补输入信号,以放大该对互补输入信号之间的电压差。 场效应晶体管锁存电路响应双极晶体管电压增益输入缓冲器,锁存经过放大的电压差,从而产生一对互补输出信号。

    Nonvolatile memory device and related method of operation
    2.
    发明授权
    Nonvolatile memory device and related method of operation 有权
    非易失存储器件及相关操作方法

    公开(公告)号:US07586775B2

    公开(公告)日:2009-09-08

    申请号:US11850130

    申请日:2007-09-05

    CPC classification number: G11C13/0069 G11C13/0004 G11C2013/009

    Abstract: A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater than the first magnitude. The first circuit block selectively receives the first voltage or the second voltage through an input node. The discharge unit discharges the input node between a time point where the input node has been charged with the second voltage and a time point where the input node receives the first voltage.

    Abstract translation: 非易失性存储器件包括第一电压产生单元,第二电压产生单元,第一电路块和放电单元。 第一电压产生单元产生具有第一量值的第一电压。 第二电压产生单元产生具有大于第一幅值的第二幅度的第二电压。 第一电路块通过输入节点选择性地接收第一电压或第二电压。 放电单元在输入节点已经被充电的时间点与第二电压之间和输入节点接收到第一电压的时间点之间对输入节点进行放电。

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