公开(公告)号：US06707704B2

公开(公告)日：2004-03-16

申请号：US10392843

申请日：2003-03-21

申请人： Yoshihisa Kato ,  Yasuhiro Shimada ,  Takayoshi Yamada

发明人： Yoshihisa Kato ,  Yasuhiro Shimada ,  Takayoshi Yamada

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： The semiconductor memory device of the invention includes at least three memory cell blocks arranged in a word line direction. Each of the memory cell blocks includes a plurality of memory cells arranged in a bit line direction. Each of the memory cells includes a ferroelectric capacitor for storing data by displacement of polarization of a ferroelectric film and a selection transistor connected to one of paired electrodes of the ferroelectric capacitor. Each of the memory cell blocks also includes: a bit line, a sub-bit line and a source line extending in the bit line direction; and a read transistor having a gate connected to one end of the sub-bit line, a source connected to the source line, and a drain connected to one end of the bit line. The read transistor reads data by detecting the displacement of the polarization of the ferroelectric film of the ferroelectric capacitor of a data read memory cell from which data is read among the plurality of memory cells. The sub-bit lines of any two of the memory cell blocks are connected to each other via a sub-bit line coupling switch.

摘要翻译： 本发明的半导体存储器件包括沿字线方向布置的至少三个存储单元块。 每个存储单元块包括以位线方向排列的多个存储单元。 每个存储单元包括用于通过铁电薄膜的极化位移存储数据的铁电电容器和连接到铁电体电容器的一对电极之一的选择晶体管。 每个存储单元块还包括：位线，子位线和沿位线方向延伸的源极线; 以及读取晶体管，其具有连接到子位线的一端的栅极，连接到源极线的源极和连接到位线的一端的漏极。 读取晶体管通过检测在多个存储单元中从其读取数据的数据读取存储单元的铁电电容器的铁电体的极化的位移来读取数据。 任何两个存储单元块的子位线通过子位线耦合开关相互连接。

公开(公告)号：US06950327B2

公开(公告)日：2005-09-27

申请号：US10686583

申请日：2003-10-17

申请人： Yasuhiro Shimada ,  Yoshihisa Kato ,  Takayoshi Yamada

发明人： Yasuhiro Shimada ,  Yoshihisa Kato ,  Takayoshi Yamada

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： In a ferroelectric capacitor, two displacements (points b and c) of a remanent polarization correspond to data “1” and one displacement (point a) of the remanent polarization corresponds to data “0”. When the data “1” is written, either of two electric voltage pulses different in potential or in pulse width is applied to the ferroelectric capacitor to position the displacement of the remanent polarization in the ferroelectric capacitor at the point b or at the point c. When the data “0” is written, on the other hand, the displacement of the remanent polarization in the ferroelectric capacitor is positioned at the point a.

摘要翻译： 在铁电电容器中，剩余极化的两个位移（点b和c）对应于数据“1”，剩余极化的一个位移（点a）对应于数据“0”。 当写入数据“1”时，电压或脉冲宽度不同的两个电压脉冲中的任一个施加到铁电电容器，以将铁电电容器中剩余极化的位移定位在点b处或点c处。 另一方面，当写入数据“0”时，铁电电容器中剩余极化的位移位于点a处。

公开(公告)号：US06853576B2

公开(公告)日：2005-02-08

申请号：US10653201

申请日：2003-09-03

申请人： Yoshihisa Kato ,  Yasuhiro Shimada ,  Takayoshi Yamada

发明人： Yoshihisa Kato ,  Yasuhiro Shimada ,  Takayoshi Yamada

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/22

CPC分类号： G11C11/22 ,  G11C7/1048 ,  G11C7/12

摘要： A semiconductor memory device has a plurality of memory cells each having a first ferroelectric capacitor for storing data as a polarization value. First voltage applying means applies a first read voltage between the pair of electrodes of the first ferroelectric capacitor composing that one of the plurality of memory cells from which data is to be read. Data reading means detects the polarization value in the first ferroelectric capacitor when the first read voltage is applied between the pair of electrodes of the first ferroelectric capacitor and thereby reads the data stored in the first ferroelectric capacitor therefrom. A hysteresis loop in the first ferroelectric capacitor is shifted in a direction of voltage opposite in polarity to the first read voltage.

摘要翻译： 半导体存储器件具有多个存储单元，每个存储单元具有用于存储数据作为极化值的第一铁电电容器。 第一电压施加装置在构成要从其读取数据的多个存储单元中的一个的第一强电介质电容器的一对电极之间施加第一读取电压。 当在第一强电介质电容器的一对电极之间施加第一读取电压时，数据读取装置检测第一铁电电容器中的极化值，从而读取存储在第一铁电电容器中的数据。 第一铁电电容器中的磁滞回线在与第一读取电压的极性相反的电压方向上偏移。

公开(公告)号：US06753560B2

公开(公告)日：2004-06-22

申请号：US09891214

申请日：2001-06-26

申请人： Yoshihisa Kato ,  Yasuhiro Shimada

发明人： Yoshihisa Kato ,  Yasuhiro Shimada

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L28/55

摘要： A semiconductor memory of this invention is composed of an MFMIS transistor including a first field effect transistor and a ferroelectric capacitor formed on or above the first field effect transistor with a gate electrode of the first field effect transistor working as or being electrically connected to a lower electrode of the ferroelectric capacitor, an upper electrode of the ferroelectric capacitor working as a control gate and the first field effect transistor having a first well region; and a second field effect transistor having a second well region that is isolated from the first well region of the first field effect transistor. The first well region of the first field effect transistor is electrically connected to the source region of the second field effect transistor, and the gate electrode of the first field effect transistor is electrically connected to the drain region of the second field effect transistor.

摘要翻译： 本发明的半导体存储器由包括形成在第一场效应晶体管上或第一场效应晶体管上的第一场效应晶体管和铁电电容器的MFMIS晶体管组成，其中第一场效应晶体管的栅电极用作或与下电 铁电电容器的电极，作为控制栅极的铁电电容器的上电极和具有第一阱区的第一场效应晶体管; 以及具有与第一场效应晶体管的第一阱区隔离的第二阱区的第二场效应晶体管。 第一场效应晶体管的第一阱区电连接到第二场效应晶体管的源极区域，第一场效应晶体管的栅极电连接到第二场效应晶体管的漏极区域。

公开(公告)号：US06449185B2

公开(公告)日：2002-09-10

申请号：US09886995

申请日：2001-06-25

申请人： Yoshihisa Kato ,  Yasuhiro Shimada

发明人： Yoshihisa Kato ,  Yasuhiro Shimada

IPC分类号： G11C1122

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

摘要： A semiconductor memory includes a storing transistor for storing data, wherein the storing transistor includes an MFS transistor, an MFIS transistor, or an MFMIS transistor, and a selecting transistor for selecting the storing transistor. The storing transistor is a first field effect transistor having a first well region. The selecting transistor is second field effect transistor having a second well region that is isolated from the first well region of the first field effect transistor. The semiconductor memory further includes a first voltage supply line for supplying a DC voltage to the first well region of the first field effect transistor, and a second voltage supply line, independent of the first voltage supply line, for supplying a DC voltage to the second well region of the second field effect transistor.

摘要翻译： 半导体存储器包括用于存储数据的存储晶体管，其中存储晶体管包括MFS晶体管，MFIS晶体管或MFMIS晶体管，以及用于选择存储晶体管的选择晶体管。 存储晶体管是具有第一阱区的第一场效应晶体管。 选择晶体管是具有与第一场效应晶体管的第一阱区隔离的第二阱区的第二场效应晶体管。 半导体存储器还包括用于向第一场效应晶体管的第一阱区域提供DC电压的第一电压供应线和独立于第一电压供应线的第二电压供应线，用于向第二场效应晶体管提供DC电压 第二场效应晶体管的阱区。

公开(公告)号：US06421268B2

公开(公告)日：2002-07-16

申请号：US09899839

申请日：2001-07-09

申请人： Yoshihisa Kato ,  Yasuhiro Shimada

发明人： Yoshihisa Kato ,  Yasuhiro Shimada

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A multi-valued data is written in a ferroelectric capacitor, which stores a multi-valued data in accordance with displacement of polarization of a ferroelectric film thereof, by applying a relatively high first writing voltage or a relatively low second writing voltage between a first electrode and a second electrode of the ferroelectric capacitor. Next, a potential difference induced between the first and second electrodes is removed. Then, the multi-valued data is read by detecting the displacement of the polarization of the ferroelectric film by applying a reading voltage between the second electrode and a substrate where a reading FET for detecting the displacement of the polarization of the ferroelectric film is formed. The reading voltage has the same polarity as the first writing voltage and is set to such magnitude that, in applying the reading voltage, a first potential difference induced between the gate electrode of the reading FET and the substrate when the multi-valued data is written by applying the first writing voltage is smaller than a second potential difference induced between the gate electrode and the substrate when the multi-valued data is written by applying the second writing voltage.

摘要翻译： 多值数据被写入铁电电容器中，该铁电电容器通过在第一电极之间施加相对较高的第一写入电压或相对较低的第二写入电压来存储根据其铁电体膜的极化位移的多值数据 和铁电电容器的第二电极。 接下来，去除在第一和第二电极之间引起的电位差。 然后，通过在第二电极和衬底之间施加读取电压来检测强电介质膜的偏振的位移来读取多值数据，其中形成用于检测强电介质膜的偏振位移的读取FET。 读取电压具有与第一写入电压相同的极性，并且被设置为使得在施加读取电压时，当写入多值数据时，在读取FET的栅电极和衬底之间感应的第一电位差 通过施加第一写入电压小于通过施加第二写入电压来写入多值数据时在栅电极和衬底之间感应的第二电位差。

公开(公告)号：US20060095975A1

公开(公告)日：2006-05-04

申请号：US11212585

申请日：2005-08-29

申请人： Takayoshi Yamada ,  Shinzo Koyama ,  Yoshihisa Kato ,  Yasuhiro Shimada

发明人： Takayoshi Yamada ,  Shinzo Koyama ,  Yoshihisa Kato ,  Yasuhiro Shimada

IPC分类号： H04L9/32

CPC分类号： G06F21/79 ,  H04L9/085

摘要： A semiconductor device of the present invention includes: at least one of non-volatile memory unit operable to store data; at least one of an arithmetic-logic unit operable to perform an arithmetic-logic operation using data which is stored in the memory unit and data that is inputted from outside; and an output unit operable to output a result of arithmetic-logic operation performed by the arithmetic-logic unit; wherein the memory unit, the arithmetic-logic unit, and the output unit are included in a functional block, and an output line of each of the memory unit is connected only to one of at least one of the arithmetic-logic unit.

摘要翻译： 本发明的半导体器件包括：用于存储数据的非易失性存储单元中的至少一个; 算术逻辑单元中的至少一个，其可操作以使用存储在存储单元中的数据和从外部输入的数据执行算术运算; 以及输出单元，其可操作以输出由所述算术单元执行的算术逻辑运算的结果; 其中所述存储器单元，所述算术逻辑单元和所述输出单元包括在功能块中，并且所述存储器单元中的每一个的输出线仅与所述算术单元中的至少一个连接。

公开(公告)号：US06924997B2

公开(公告)日：2005-08-02

申请号：US10381235

申请日：2001-09-25

申请人： Zheng Chen ,  Vikram Joshi ,  Myoungho Lim ,  Carlos A. Paz de Araujo ,  Larry D. McMillan ,  Yoshihisa Kato ,  Tatsuo Otsuki ,  Yasuhiro Shimada

发明人： Zheng Chen ,  Vikram Joshi ,  Myoungho Lim ,  Carlos A. Paz de Araujo ,  Larry D. McMillan ,  Yoshihisa Kato ,  Tatsuo Otsuki ,  Yasuhiro Shimada

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.

摘要翻译： 铁电存储器636包括一组存储单元（645,12,21,301,401,501），每个单元具有铁电存储元件（44,218等），驱动线（122,322,422， 522等），在其上放置用于将信息写入到存储器单元组的电压，位线（25,49,125,325,425,525等），其中要从该组存储器单元读出的信息 放置存储器单元，在存储器单元和位线之间的前置放大器（20,42,120,320,420等），连接在存储器单元之间的设定开关（14,114,314,414,514等） 驱动线和存储器单元，以及与前置放大器并联连接到存储器单元的复位开关（16,116,316,416,516等）。 通过将小于铁电存储元件的矫顽电压的电压放置在存储元件上来读取存储器。 在读取之前，通过使铁电存储元件的两个电极接地来放电来自该组电池的噪声。

公开(公告)号：US06614678B2

公开(公告)日：2003-09-02

申请号：US09905893

申请日：2001-07-17

申请人： Yoshihisa Kato ,  Yasuhiro Shimada

发明人： Yoshihisa Kato ,  Yasuhiro Shimada

IPC分类号： G11C1122

CPC分类号： G11C11/22 ,  G11C11/223

摘要： A semiconductor memory of this invention contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of the successively connected plural ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a ferroelectric capacitor selected from the plural ferroelectric capacitors. A set line is connected to the other end of the successively connected plural ferroelectric capacitors. A bit line is connected to the drain of the reading transistor at one end thereof. A reset line is connected to the source of the reading transistor at one end thereof. A plurality of word lines respectively corresponding to the plural ferroelectric capacitors are provided perpendicularly to the bit line, so as to select a ferroelectric capacitor from the plural ferroelectric capacitors for data write or data read.

公开(公告)号：US06456520B1

公开(公告)日：2002-09-24

申请号：US09941736

申请日：2001-08-30

申请人： Yoshihisa Kato ,  Yasuhiro Shimada

发明人： Yoshihisa Kato ,  Yasuhiro Shimada

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： The semiconductor memory of this invention includes a plurality of ferroelectric capacitors successively connected to one another in a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof; a plurality of selecting transistors respectively connected to the plurality of ferroelectric capacitor in parallel for selecting a selected ferroelectric capacitor from the plural ferroelectric capacitors; a set line connected to a first end of a series circuit including the plural successively connected ferroelectric capacitors to which a reading voltage is applied; and a load capacitor connected to a second end of the series circuit for detecting displacement of polarization of the ferroelectric film of the selected ferroelectric capacitor. In the series circuit, capacitance is larger in a ferroelectric capacitor disposed in a position relatively near to the first end of the series circuit than in a ferroelectric capacitor disposed in a position relatively far from the first end.

摘要翻译： 本发明的半导体存储器包括在位线方向上相继连接的多个铁电电容器，用于根据其铁电体膜的极化位移来存储数据; 分别与所述多个铁电电容器并联连接的多个选择晶体管，用于从所述多个铁电电容器中选择所选择的铁电电容器; 连接到串联电路的第一端的设定线，该串联电路包括多个依次连接的强电介质电容器，其中施加了读取电压; 连接到串联电路的第二端的负载电容器，用于检测所选铁电电容器的铁电体膜的极化位移。 在串联电路中，布置在比串联电路的第一端更靠近串联电路的第一端的铁电电容器中的电容大于布置在距第一端相对较远的位置的铁电电容器中的电容。