公开(公告)号：US20080116758A1

公开(公告)日：2008-05-22

申请号：US11966089

申请日：2007-12-28

Applicant: Naoto SESITA ,  Katuyuki TANAKA ,  Yusuke MIZUKOSHI ,  Hiroyuki KURIHARA ,  Yoshihisa WATANABE ,  Kazuhito YOKOMORI

Inventor： Naoto SESITA ,  Katuyuki TANAKA ,  Yusuke MIZUKOSHI ,  Hiroyuki KURIHARA ,  Yoshihisa WATANABE ,  Kazuhito YOKOMORI

IPC: H02K1/17 ,  H02K1/18

CPC classification number: H02K5/10 ,  H02K5/15 ,  H02K5/24 ,  H02K7/081 ,  H02K7/1166 ,  H02K15/14 ,  H02K2213/09 ,  Y10T74/19828

Abstract: A motor comprises a rotor fixed to a shaft and a stator comprising a permanent magnet on the inner circumferential surface of a motor casing. The shaft extends from the opening end of the motor casing and has a worm wheel in a gear casing. The end face of the gear casing has an annular projection. The motor casing has an outward flange at the opening end. When the motor casing is connected with the gear casing, an elastic O-ring is fitted between a space formed by the outer circumferential surface of the annular projection, an outer vertical seat face of the gear casing and a corner of the outward flange thereby achieving suitable alignment of the motor casing with the gear casing. The permanent magnet is made of Nd magnet which is pressingly fitted on the inner circumferential surface of the motor casing.

Abstract translation: 电动机包括固定到轴的转子和在电机壳体的内周面上包括永磁体的定子。 轴从马达壳体的开口端延伸，并在蜗轮壳体中具有蜗轮。 齿轮箱的端面具有环形突起。 马达壳体在开口端具有向外的凸缘。 当马达壳体与齿轮箱连接时，弹性O形环装配在由环形突起的外周面形成的空间，齿轮壳体的外侧垂直座面与向外凸缘的角部之间，从而实现 电动机壳体与齿轮箱的适当对准。 永磁体由压电配合在电动机壳体的内周面上的Nd磁铁制成。

公开(公告)号：US20060238060A1

公开(公告)日：2006-10-26

申请号：US11379262

申请日：2006-04-19

Applicant: Naoto SESITA ,  Katuyuki TANAKA ,  Yusuke MIZUKOSHI ,  Hiroyuki KURIHARA ,  Yoshihisa WATANABE ,  Hiroshi SATO

Inventor： Naoto SESITA ,  Katuyuki TANAKA ,  Yusuke MIZUKOSHI ,  Hiroyuki KURIHARA ,  Yoshihisa WATANABE ,  Hiroshi SATO

IPC: H02K1/00 ,  H02K23/26 ,  H01R39/32

CPC classification number: H02K23/26 ,  H02K23/66

Abstract: A motor comprises a yoke as casing, a shaft extending along a center of the yoke, an annular stator fixed to the yoke and an armature fixed to the shaft to rotate with the shaft inside the stator. The armature comprises a plurality of teeth on the outer circumferential surface. A wire is wound on any of the teeth to form a normal coil. Another wire is wound on another of the teeth to form a brake coil that is a short circuit. When the motor rotates much faster, the brake coil produces magnetic flux which acts as load against the rotation of the motor to allow the motor to rotate slower.

Abstract translation: 马达包括作为壳体的轭，沿轭的中心延伸的轴，固定到轭的环形定子和固定到轴的电枢，其中定子内的轴旋转。 电枢包括在外圆周表面上的多个齿。 电线缠绕在任何齿上以形成正常线圈。 另一根线缠绕在另一个齿上，形成短路的制动线圈。 当马达旋转得更快时，制动线圈产生磁通，其作为负载抵抗马达的旋转的载荷，以允许马达转动较慢。

公开(公告)号：US20100124113A1

公开(公告)日：2010-05-20

申请号：US12621913

申请日：2009-11-19

Applicant: Yoshihisa WATANABE

Inventor： Yoshihisa WATANABE

IPC: G11C16/04 ,  G11C7/10 ,  G11C7/00

CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A semiconductor memory write method which, when writing data at a threshold voltage level in a memory cell, is configured to perform two write operations including a preliminary data write operation of writing temporary data at a threshold voltage level lower than that of the data at the threshold voltage level, and a final data write operation of additionally writing final data at the threshold voltage level, includes making at least one of a write time of the preliminary data write operation, a word-line waiting time of verify read, and a bit-line waiting time of verify read, shorter than that of the final data write operation.

Abstract translation: 一种半导体存储器写入方法，当在存储器单元中以阈值电压电平写入数据时，被配置为执行两个写入操作，所述写入操作包括以比在该存储器单元的数据的阈值电压电平低的阈值电压写入临时数据的初步数据写入操作 以及在阈值电压电平附加地写入最终数据的最终数据写入操作包括进行初步数据写入操作的写入时间，验证读取的字线等待时间和位的至少一个 线路等待时间验证读取，比最终数据写入操作更短。

公开(公告)号：US20110069546A1

公开(公告)日：2011-03-24

申请号：US12885911

申请日：2010-09-20

Applicant: Yoshihisa WATANABE

Inventor： Yoshihisa WATANABE

IPC: G11C16/04 ,  G11C16/12

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells to store N-value data (N being an integer equal to or larger than 3); and a writing circuit configured to repeatedly execute a writing cycle on a plurality of memory cells until data writing is finished. The writing circuit divides the pulse width of the writing pulse into a plurality of sections to change the pulse height among the sections such that the respective sections provide writing voltages for writing different target threshold levels, and brings the bit line connected to the memory cell to be written with any of the target threshold levels into a selected state synchronously to the section for applying the writing voltage for writing that target threshold level.

Abstract translation: 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括存储N值数据（N为等于或大于3的整数）的多个存储单元; 以及写入电路，被配置为在数据写入结束之前重复地执行多个存储单元上的写入周期。 写入电路将写入脉冲的脉冲宽度分割成多个部分，以改变这些部分之间的脉冲高度，使得各个部分提供用于写入不同目标阈值电平的写入电压，并且将连接到存储器单元的位线 与用于写入该目标阈值电平的写入电压的部分同步地将任何目标阈值电平写入选定状态。

公开(公告)号：US20100177570A1

公开(公告)日：2010-07-15

申请号：US12683022

申请日：2010-01-06

Applicant: Yoshihisa WATANABE

Inventor： Yoshihisa WATANABE

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage generating circuit is supplied to one end of the current path and the gate of the first transistor. The first transistor outputs the program voltage from the other end of the current path thereof. A driving transistor has one end of a current path thereof connected to a word line, and has a gate supplied with the first voltage. The driving transistor has the other end of the current path supplied with the program voltage. Stress applying portion applies the erase voltage to the other end of the current path of the first transistor at the time of erase.

Abstract translation: 电压产生电路在写入时产生高于编程电压的第一电压，并在擦除时产生擦除电压。 第一晶体管具有电流路径和栅极，并且由电压产生电路产生的第一电压被提供给电流路径的一端和第一晶体管的栅极。 第一晶体管从其电流路径的另一端输出编程电压。 驱动晶体管的电流路径的一端连接到字线，并且具有提供有第一电压的栅极。 驱动晶体管具有提供有编程电压的电流通路的另一端。 应力施加部分在擦除时将擦除电压施加到第一晶体管的电流路径的另一端。

公开(公告)号：US20100165733A1

公开(公告)日：2010-07-01

申请号：US12646551

申请日：2009-12-23

Applicant: Dai NAKAMURA ,  Koichi FUKUDA ,  Yoshihisa WATANABE ,  Makoto IWAI

Inventor： Dai NAKAMURA ,  Koichi FUKUDA ,  Yoshihisa WATANABE ,  Makoto IWAI

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines respectively connected to control gate electrodes of the memory cells, a first selection transistor connected between one end of the memory cells and a source line, a second selection transistor connected between the other end of the memory cells and a bit line, and a driver configured to control voltages applied to the word lines. The driver applies a first voltage to a first word line connected to a selected memory cell, and applies a cutoff voltage that cuts off a channel of a memory cell to second word lines of a number not less than three arranged side by side on the source line side with respect to the first word line during a write operation.

Abstract translation: NAND非易失性半导体存储器包括多个串联存储单元，每个存储单元包括电荷存储层和控制栅极电极，分别连接到存储单元的控制栅电极的多条字线，连接在存储单元的一端 存储单元和源极线，连接在存储单元的另一端和位线之间的第二选择晶体管和被配置为控制施加到字线的电压的驱动器。 驱动器对连接到所选择的存储单元的第一字线施加第一电压，并且将截止电压切断到存储单元的通道的截止电压到源于并排布置在源上的不少于三个的数量的第二字线 在写入操作期间相对于第一字线的线侧。