公开(公告)号：US08929774B2

公开(公告)日：2015-01-06

申请号：US13312596

申请日：2011-12-06

Applicant: Tsutomu Katoh ,  Yohhei Watanabe ,  Yuji Kato ,  Yoshihisa Watanabe ,  Hajime Teraji ,  Arinobu Yoshiura

Inventor： Tsutomu Katoh ,  Yohhei Watanabe ,  Yuji Kato ,  Yoshihisa Watanabe ,  Hajime Teraji ,  Arinobu Yoshiura

IPC: G03G15/08 ,  G03G15/00 ,  G03G15/16

CPC classification number: G03G15/1615 ,  G03G2215/0129

Abstract: A belt unit is detachably attached to a housing. A holder changes a state of an endless belt by moving a transfer roller between a first state as an endless belt movement state and a second state as a detachment state. The first state allows the endless belt to circulate for image formation, and the second state allows the belt unit to be detached from the housing. The holder moves the transfer roller adjacent supporter independently of the transfer roller and lifts the opening in the endless belt to a prescribed position to expose it to the front side plate.

Abstract translation: 带单元可拆卸地附接到壳体。 支架通过将转印辊移动到作为环形带移动状态的第一状态和作为分离状态的第二状态之间来改变环形带的状态。 第一状态允许环形带循环用于图像形成，并且第二状态允许带单元与壳体分离。 保持器独立于转印辊移动转印辊与支撑件相邻，并将环形带中的开口提升到规定位置以将其暴露于前侧板。

公开(公告)号：US07924621B2

公开(公告)日：2011-04-12

申请号：US12544284

申请日：2009-08-20

Applicant: Yuka Furuta ,  Yoshihisa Watanabe

Inventor： Yuka Furuta ,  Yoshihisa Watanabe

IPC: G11C16/00

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.

Abstract translation: 一种控制NAND型闪速存储器的方法，该闪存具有临时存储数据的锁存电路，在锁存电路被保留第一逻辑的第一状态下测量锁存电路的第一消耗电流; 在第二状态下测量锁存电路的第二消耗电流，其中使得所述锁存电路保持通过反转所述第一逻辑而获得的第二逻辑; 以及比较所述第一消耗电流和所述第二消耗电流以使所述锁存电路保持与所述第一消耗电流和所述第二消耗电流中的较小的一个相对应的状态。

公开(公告)号：US20110069546A1

公开(公告)日：2011-03-24

申请号：US12885911

申请日：2010-09-20

Applicant: Yoshihisa WATANABE

Inventor： Yoshihisa WATANABE

IPC: G11C16/04 ,  G11C16/12

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells to store N-value data (N being an integer equal to or larger than 3); and a writing circuit configured to repeatedly execute a writing cycle on a plurality of memory cells until data writing is finished. The writing circuit divides the pulse width of the writing pulse into a plurality of sections to change the pulse height among the sections such that the respective sections provide writing voltages for writing different target threshold levels, and brings the bit line connected to the memory cell to be written with any of the target threshold levels into a selected state synchronously to the section for applying the writing voltage for writing that target threshold level.

Abstract translation: 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括存储N值数据（N为等于或大于3的整数）的多个存储单元; 以及写入电路，被配置为在数据写入结束之前重复地执行多个存储单元上的写入周期。 写入电路将写入脉冲的脉冲宽度分割成多个部分，以改变这些部分之间的脉冲高度，使得各个部分提供用于写入不同目标阈值电平的写入电压，并且将连接到存储器单元的位线 与用于写入该目标阈值电平的写入电压的部分同步地将任何目标阈值电平写入选定状态。

公开(公告)号：US20100303485A1

公开(公告)日：2010-12-02

申请号：US12790116

申请日：2010-05-28

Applicant: Yoshihisa Watanabe

Inventor： Yoshihisa Watanabe

IPC: G03G15/00 ,  G03G15/16 ,  G03G15/01

CPC classification number: G03G15/1605 ,  G03G15/1675 ,  G03G2215/0129

Abstract: An image forming apparatus includes a receiver to receive image information from an external device, a movable intermediate transfer member, a plurality of latent image bearing members on which a latent image is formed based on the image information, a plurality of developing devices, each of which disposed in proximity to the latent image baring member, to develop the latent image on the latent image bearing member with toner to form a toner image thereon, a transfer bias application mechanism to apply a transfer bias to the intermediate transfer member and halt temporarily and periodically application of the transfer bias in a continuous output mode in which a plurality of images are continuously formed on different recording media sheets based on the image information of the plurality of images received continuously by the receiver, and a secondary transfer member to transfer the superimposed toner image onto a recording medium.

Abstract translation: 图像形成装置包括从外部装置接收图像信息的接收器，可移动中间转印部件，基于图像信息形成有潜像的多个潜像承载部件，多个显影装置， 其设置在潜像保护构件附近，以通过调色剂在潜像承载部件上显影以在其上形成调色剂图像;转印偏压施加机构，用于向中间转印部件施加转印偏压并暂时停止; 基于由接收器连续接收的多个图像的图像信息，在连续输出模式中周期性地施加转印偏压，其中多个图像被连续地形成在不同的记录介质片上，以及二次转印部件， 调色剂图像到记录介质上。

公开(公告)号：US20100177570A1

公开(公告)日：2010-07-15

申请号：US12683022

申请日：2010-01-06

Applicant: Yoshihisa WATANABE

Inventor： Yoshihisa WATANABE

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A voltage generating circuit generates, at a time of write, a first voltage which is higher than a program voltage, and generates an erase voltage at a time of erase. A first transistor has a current path and a gate, and the first voltage generated by the voltage generating circuit is supplied to one end of the current path and the gate of the first transistor. The first transistor outputs the program voltage from the other end of the current path thereof. A driving transistor has one end of a current path thereof connected to a word line, and has a gate supplied with the first voltage. The driving transistor has the other end of the current path supplied with the program voltage. Stress applying portion applies the erase voltage to the other end of the current path of the first transistor at the time of erase.

Abstract translation: 电压产生电路在写入时产生高于编程电压的第一电压，并在擦除时产生擦除电压。 第一晶体管具有电流路径和栅极，并且由电压产生电路产生的第一电压被提供给电流路径的一端和第一晶体管的栅极。 第一晶体管从其电流路径的另一端输出编程电压。 驱动晶体管的电流路径的一端连接到字线，并且具有提供有第一电压的栅极。 驱动晶体管具有提供有编程电压的电流通路的另一端。 应力施加部分在擦除时将擦除电压施加到第一晶体管的电流路径的另一端。

公开(公告)号：US20100165733A1

公开(公告)日：2010-07-01

申请号：US12646551

申请日：2009-12-23

Applicant: Dai NAKAMURA ,  Koichi FUKUDA ,  Yoshihisa WATANABE ,  Makoto IWAI

Inventor： Dai NAKAMURA ,  Koichi FUKUDA ,  Yoshihisa WATANABE ,  Makoto IWAI

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: A NAND nonvolatile semiconductor memory includes a plurality of series-connected memory cells each includes a charge storage layer and control gate electrode, a plurality of word lines respectively connected to control gate electrodes of the memory cells, a first selection transistor connected between one end of the memory cells and a source line, a second selection transistor connected between the other end of the memory cells and a bit line, and a driver configured to control voltages applied to the word lines. The driver applies a first voltage to a first word line connected to a selected memory cell, and applies a cutoff voltage that cuts off a channel of a memory cell to second word lines of a number not less than three arranged side by side on the source line side with respect to the first word line during a write operation.

Abstract translation: NAND非易失性半导体存储器包括多个串联存储单元，每个存储单元包括电荷存储层和控制栅极电极，分别连接到存储单元的控制栅电极的多条字线，连接在存储单元的一端 存储单元和源极线，连接在存储单元的另一端和位线之间的第二选择晶体管和被配置为控制施加到字线的电压的驱动器。 驱动器对连接到所选择的存储单元的第一字线施加第一电压，并且将截止电压切断到存储单元的通道的截止电压到源于并排布置在源上的不少于三个的数量的第二字线 在写入操作期间相对于第一字线的线侧。

公开(公告)号：US20100124128A1

公开(公告)日：2010-05-20

申请号：US12556219

申请日：2009-09-09

Applicant: Osamu NAGAO ,  Yoshihisa Watanabe ,  Koichi Fukuda

Inventor： Osamu NAGAO ,  Yoshihisa Watanabe ,  Koichi Fukuda

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/16

Abstract: A NAND flash memory in which data is erased in blocks, has a plurality of memory cell transistors provided in each of the blocks, the memory cell transistor having a floating gate which is formed via a first gate insulating film on a well formed on a semiconductor substrate and a control gate which is formed on the floating gate via a second gate insulating film, and being capable of rewriting data by controlling an amount of charge accumulated on the floating gate; and a row decoder having a plurality of n-type transfer MOS transistors having drains respectively connected to word lines respectively connected to the control gates of the plurality of memory cell transistors, the row decoder controlling gate voltages and source voltages of the transfer MOS transistors.

Abstract translation: 其中以块为单位擦除数据的NAND闪速存储器具有设置在每个块中的多个存储单元晶体管，存储单元晶体管具有浮置栅极，该浮置栅极通过形成在半导体上的阱上的第一栅极绝缘膜形成 基板和控制栅极，其经由第二栅极绝缘膜形成在浮置栅极上，并且能够通过控制在浮动栅极上累积的电荷量来重写数据; 以及具有多个n型传输MOS晶体管的行解码器，其具有分别连接到分别连接到所述多个存储单元晶体管的控制栅极的字线的漏极，所述行解码器控制所述传输MOS晶体管的栅极电压和源极电压。

公开(公告)号：US20100067302A1

公开(公告)日：2010-03-18

申请号：US12544284

申请日：2009-08-20

Applicant: Yuka FURUTA ,  Yoshihisa Watanabe

Inventor： Yuka FURUTA ,  Yoshihisa Watanabe

IPC: G11C16/04 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.

Abstract translation: 一种控制NAND型闪速存储器的方法，该闪存具有临时存储数据的锁存电路，在锁存电路被保留第一逻辑的第一状态下测量锁存电路的第一消耗电流; 在第二状态下测量锁存电路的第二消耗电流，其中使得所述锁存电路保持通过反转所述第一逻辑而获得的第二逻辑; 以及比较所述第一消耗电流和所述第二消耗电流以使所述锁存电路保持与所述第一消耗电流和所述第二消耗电流中的较小的一个相对应的状态。

公开(公告)号：US07573171B2

公开(公告)日：2009-08-11

申请号：US11379667

申请日：2006-04-21

Applicant: Naoto Sesita ,  Katuyuki Tanaka ,  Yusuke Mizukoshi ,  Hiroyuki Kurihara ,  Yoshihisa Watanabe

Inventor： Naoto Sesita ,  Katuyuki Tanaka ,  Yusuke Mizukoshi ,  Hiroyuki Kurihara ,  Yoshihisa Watanabe

IPC: H02K21/00

CPC classification number: H02K23/36 ,  H02K7/106 ,  H02K7/1166 ,  Y10T74/19828

Abstract: A rotation control motor comprises a shaft, an armature having an armature core of which teeth are wound by wires to form coils, a commutator, and a field magnet. The armature core has a plurality of teeth, the commutator has a plurality of commutator segments corresponding to the number of teeth, and the coils comprise a normal coil and a brake coil. When the motor rotates faster than expected, the brake coil brakes the motor by magnetic flux, and the motor can rotate within a stable speed range.

Abstract translation: 旋转控制电动机包括轴，具有电枢铁芯的电枢，电枢铁芯通过电线缠绕，以形成线圈，换向器和场磁体。 电枢铁芯具有多个齿，换向器具有与齿数对应的多个换向片，线圈包括正常线圈和制动线圈。 当电机转速比预期的要快时，制动线圈通过磁通量制动马达，电机可以在稳定的转速范围内旋转。

公开(公告)号：US07511396B2

公开(公告)日：2009-03-31

申请号：US11379262

申请日：2006-04-19

Applicant: Naoto Sesita ,  Katuyuki Tanaka ,  Yusuke Mizukoshi ,  Hiroyuki Kurihara ,  Yoshihisa Watanabe ,  Hiroshi Sato

Inventor： Naoto Sesita ,  Katuyuki Tanaka ,  Yusuke Mizukoshi ,  Hiroyuki Kurihara ,  Yoshihisa Watanabe ,  Hiroshi Sato

IPC: H02K1/00

CPC classification number: H02K23/26 ,  H02K23/66

Abstract: A motor comprises a yoke as casing, a shaft extending along a center of the yoke, an annular stator fixed to the yoke and an armature fixed to the shaft to rotate with the shaft inside the stator. The armature comprises a plurality of teeth on the outer circumferential surface. A wire is wound on any of the teeth to form a normal coil. Another wire is wound on another of the teeth to form a brake coil that is a short circuit. When the motor rotates much faster, the brake coil produces magnetic flux which acts as load against the rotation of the motor to allow the motor to rotate slower.

Abstract translation: 马达包括作为壳体的轭，沿轭的中心延伸的轴，固定到轭的环形定子和固定到轴的电枢，其中定子内的轴旋转。 电枢包括在外圆周表面上的多个齿。 电线缠绕在任何齿上以形成正常线圈。 另一根线缠绕在另一个齿上，形成短路的制动线圈。 当马达旋转得更快时，制动线圈产生磁通，其作为负载抵抗马达的旋转的载荷，以允许马达转动较慢。