公开(公告)号：US20090237989A1

公开(公告)日：2009-09-24

申请号：US12476536

申请日：2009-06-02

申请人： Yoshinori OKUMURA ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori OKUMURA ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (1/3)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

公开(公告)号：US20080266939A1

公开(公告)日：2008-10-30

申请号：US12213505

申请日：2008-06-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/02

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US07554837B2

公开(公告)日：2009-06-30

申请号：US12213505

申请日：2008-06-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/10

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

公开(公告)号：US07180773B2

公开(公告)日：2007-02-20

申请号：US11253696

申请日：2005-10-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US20060087874A1

公开(公告)日：2006-04-27

申请号：US11253696

申请日：2005-10-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C5/06

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US07403415B2

公开(公告)日：2008-07-22

申请号：US11698872

申请日：2007-01-29

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2 )≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1 /L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

公开(公告)号：US20070139999A1

公开(公告)日：2007-06-21

申请号：US11698872

申请日：2007-01-29

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (1/3)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

公开(公告)号：US06770522B2

公开(公告)日：2004-08-03

申请号：US10444959

申请日：2003-05-27

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： H01L218238

CPC分类号： H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052

摘要： A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electric characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed is provided. An active layer is formed by performing an additional impurity injection on a part where a sidewall insulating film is removed in a forming portion of a shared contact plug. An insulating film is laminated in a high voltage circuit part and a sidewall insulating film of wide width is formed. According to this, a forming width of a sidewall insulating film can be made small in a MOS transistor for a memory cell part, and a forming width of a sidewall insulating film can be made large in a MOS transistor for a high voltage circuit part. Thereupon, in the high voltage circuit part, a source/drain active layer can be formed in the position more distant from a gate electrode.

摘要翻译： 一种半导体器件及其制造方法，其适用于在一个半导体基板上形成用于存储单元的晶体管和高电压电路部分的晶体管，此外，在侧壁 提供了共享接触插塞部件中的绝缘膜。 通过在共享接触插塞的形成部分中去除侧壁绝缘膜的部分上执行附加杂质注入来形成有源层。 在高压电路部分层叠绝缘膜，形成宽幅的侧壁绝缘膜。 因此，可以在用于存储单元部分的MOS晶体管中使侧壁绝缘膜的形成宽度小，并且在用于高电压电路部分的MOS晶体管中可以使侧壁绝缘膜的形成宽度大。 因此，在高电压电路部分中，可以在远离栅电极的位置形成源极/漏极有源层。

公开(公告)号：US08546151B2

公开(公告)日：2013-10-01

申请号：US12528854

申请日：2008-02-25

申请人： Haruo Furuta ,  Shuichi Ueno ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Takeharu Kuroiwa ,  Lien-Chang Wang ,  Eugene Chen ,  Yiming Huai

发明人： Haruo Furuta ,  Shuichi Ueno ,  Ryoji Matsuda ,  Tatsuya Fukumura ,  Takeharu Kuroiwa ,  Lien-Chang Wang ,  Eugene Chen ,  Yiming Huai

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  B82Y10/00 ,  H01L27/228

摘要： Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode. Also disclosed is a magnetic storage device comprising an interlayer insulating film provided with a wiring layer, an insulating film formed on the interlayer insulating film, an opening formed in the insulating film so that the wiring layer is exposed therefrom, a barrier metal layer provided so as to cover the inner surface of the opening, a lower electrode formed on the barrier metal so as to fill the opening, and a TMR element formed on the lower electrode.

摘要翻译： 公开了一种制造包括TMR元件的磁存储装置的方法，该方法包括在具有布线层的层间绝缘膜上形成绝缘膜的步骤，用于在绝缘膜上形成开口的开口形成步骤， 布线层暴露于其中，金属层形成步骤用于在绝缘层上形成金属层以使其开口被填充; CMP步骤，用于通过CMP方法在绝缘层上抛光和去除金属层，并形成金属 剩余在开口中的层形成下电极，以及在下电极上形成TMR元件的步骤。 还公开了一种磁存储装置，其包括设置有布线层的层间绝缘膜，形成在层间绝缘膜上的绝缘膜，形成在绝缘膜中的开口，使得布线层暴露于其中，阻挡金属层设置为 为了覆盖开口的内表面，形成在阻挡金属上以便填充开口的下电极和形成在下电极上的TMR元件。

公开(公告)号：US08258592B2

公开(公告)日：2012-09-04

申请号：US12463865

申请日：2009-05-11

申请人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

发明人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/12

摘要： A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film and a hard mask is formed over the CAP layer. The CAP layer contains a substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a substance of crystalline tantalum (Ta) as a constituent material. The film thickness of the hard mask is larger than that of the CAP layer.

摘要翻译： 提供一种具有优异的操作特性的MTJ装置的半导体装置及其制造方法。 MTJ装置由层叠结构形成，其通过依次层叠下磁性膜，隧道绝缘膜和上磁性膜而获得。 下部和上部磁性膜含有非结晶或微晶铁硼（CoFeB）作为构成材料。 隧道绝缘膜包含氧化铝（AlOx）作为构成材料。 在上磁性膜上形成CAP层，在CAP层上形成硬掩模。 CAP层包含结晶钌（Ru）作为构成材料的物质，硬掩模含有结晶钽（Ta）作为构成材料的物质。 硬掩模的膜厚大于CAP层的膜厚。