公开(公告)号：US07554837B2

公开(公告)日：2009-06-30

申请号：US12213505

申请日：2008-06-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/10

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

公开(公告)号：US07403415B2

公开(公告)日：2008-07-22

申请号：US11698872

申请日：2007-01-29

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2 )≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1 /L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

公开(公告)号：US20070139999A1

公开(公告)日：2007-06-21

申请号：US11698872

申请日：2007-01-29

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (1/3)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

公开(公告)号：US06770522B2

公开(公告)日：2004-08-03

申请号：US10444959

申请日：2003-05-27

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： H01L218238

CPC分类号： H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L27/1052

摘要： A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electric characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed is provided. An active layer is formed by performing an additional impurity injection on a part where a sidewall insulating film is removed in a forming portion of a shared contact plug. An insulating film is laminated in a high voltage circuit part and a sidewall insulating film of wide width is formed. According to this, a forming width of a sidewall insulating film can be made small in a MOS transistor for a memory cell part, and a forming width of a sidewall insulating film can be made large in a MOS transistor for a high voltage circuit part. Thereupon, in the high voltage circuit part, a source/drain active layer can be formed in the position more distant from a gate electrode.

摘要翻译： 一种半导体器件及其制造方法，其适用于在一个半导体基板上形成用于存储单元的晶体管和高电压电路部分的晶体管，此外，在侧壁 提供了共享接触插塞部件中的绝缘膜。 通过在共享接触插塞的形成部分中去除侧壁绝缘膜的部分上执行附加杂质注入来形成有源层。 在高压电路部分层叠绝缘膜，形成宽幅的侧壁绝缘膜。 因此，可以在用于存储单元部分的MOS晶体管中使侧壁绝缘膜的形成宽度小，并且在用于高电压电路部分的MOS晶体管中可以使侧壁绝缘膜的形成宽度大。 因此，在高电压电路部分中，可以在远离栅电极的位置形成源极/漏极有源层。

公开(公告)号：US20080266939A1

公开(公告)日：2008-10-30

申请号：US12213505

申请日：2008-06-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/02

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US07180773B2

公开(公告)日：2007-02-20

申请号：US11253696

申请日：2005-10-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US20060087874A1

公开(公告)日：2006-04-27

申请号：US11253696

申请日：2005-10-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C5/06

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US06300656B1

公开(公告)日：2001-10-09

申请号：US08647532

申请日：1996-05-15

申请人： Shuichi Ueno ,  Shigeru Kusunoki ,  Yoshinori Okumura

发明人： Shuichi Ueno ,  Shigeru Kusunoki ,  Yoshinori Okumura

IPC分类号： G11C1134

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/66659 ,  H01L29/7835

摘要： A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

摘要翻译： 非易失性半导体存储器件包括在p型硅衬底的表面上与n +漏极扩散区域接触并覆盖其周围的n型区域。 该器件还包括与n型区域接触并覆盖其周边的p型​​杂质区域。 n +漏极扩散区域，n型区域和p +杂质区域延伸到位于浮置栅电极正下方的区域。 由此，非易失性半导体存储器件具有能够沿着栅电极方向注入高能电子的结构。

公开(公告)号：US06815295B1

公开(公告)日：2004-11-09

申请号：US09429283

申请日：1999-10-28

申请人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

发明人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L21335

CPC分类号： H01L27/11526 ,  H01L21/76218 ,  H01L21/8234 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11546

摘要： In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more than one stages. Since doses of nitrogen are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), concentrations of nitrogen in the nitrogen-introduced regions (N1 to N3) are accordingly different from each other. Concentrations of nitrogen in the gate electrodes are progressively lower in the order of expected higher threshold values.

摘要翻译： 在根据本发明的半导体器件及其制造方法中，消除了阈值与扩散层泄漏之间的折衷关系，并且不需要在多于一个阶段形成栅极氧化膜。 由于在N沟道型MOS晶体管（T41〜T43）的栅电极（4A〜4C）之间氮的浓度彼此不同，因此导入氮区域（N1〜N3）的氮浓度因此不同 。 栅电极中的氮浓度按预期的较高阈值的顺序逐渐降低。

公开(公告)号：US6020610A

公开(公告)日：2000-02-01

申请号：US946659

申请日：1997-10-07

申请人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

发明人： Shuichi Ueno ,  Yoshinori Okumura ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/105 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11546

摘要： With a semiconductor device and according to a manufacturing method of the invention, a trade-off relationship between a threshold value and a diffusion layer leak is eliminated, and it is not necessary to form a gate oxide film at a plurality of steps. Gate electrodes (4A, 4B and 4C) respectively comprise a polysilicon layer (M1) and a WSi layer (L1), the polysilicon layer (M1) and a WSi layer (L2), the polysilicon layer (M1) and a WSi layer (L3), which are respectively stacked in this order on a gate oxide film (3). Channel dope layers (103A, 103B and 103C) are formed within a well layer (101) respectively under the gate electrodes (4A, 4B and 4C).

摘要翻译： 利用半导体器件并且根据本发明的制造方法，消除了阈值和扩散层泄漏之间的权衡关系，并且不需要在多个步骤形成栅极氧化膜。 栅极（4A，4B和4C）分别包括多晶硅层（M1）和WSi层（L1），多晶硅层（M1）和WSi层（L2），多晶硅层（M1）和WSi层 L3），它们分别按栅极氧化膜（3）层叠。 通道掺杂层（103A，103B和103C）分别在栅电极（4A，4B和4C）的阱层（101）内形成。