Exhaust manifold
    1.
    发明授权
    Exhaust manifold 失效
    排气歧管

    公开(公告)号:US4077210A

    公开(公告)日:1978-03-07

    申请号:US659407

    申请日:1976-02-19

    摘要: An exhaust manifold has dual liner structure constructed of an intermediate liner forming a chamber and a plurality of sleeves extending outwardly from the chamber and of an inner liner within the intermediate liner. The inner liner forms a reaction chamber within the chamber of the intermediate liner and a plurality of tubes extending outwardly from the reaction chamber and mounted within the sleeves, respectively. The tubes have inlet ports for connection to exhaust ports of an internal combustion engine. The reaction chamber is formed with a plurality of apertures opening to the chamber of the intermediate liner to let hot gases to flow into the chamber of the intermediate liner embracing the reaction chamber. The chamber of the intermediate liner is formed with an outlet port for connection to an exhaust pipe.

    摘要翻译: 排气歧管具有双层衬里结构,其由形成腔室的中间衬套和从腔室向外延伸的多个套筒以及中间衬套内的内衬层构成。 内衬层在中间衬套的腔室内形成反应室,并且分别从反应室向外延伸并安装在套管内的多个管。 管具有用于连接到内燃机排气口的入口。 反应室形成有通向中间衬套的室的多个孔,以使热气体流入包围反应室的中间衬套的室中。 中间衬套的腔室形成有用于连接到排气管的出口。

    SUPPORT METHOD AND DESIGN SUPPORT APPARATUS
    2.
    发明申请
    SUPPORT METHOD AND DESIGN SUPPORT APPARATUS 有权
    支持方法和设计支持设备

    公开(公告)号:US20100169851A1

    公开(公告)日:2010-07-01

    申请号:US12642044

    申请日:2009-12-18

    IPC分类号: G06F17/50

    摘要: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

    摘要翻译: 一种设计支持方法,用于使计算机使用布局数据来提供宏单元布置的布局,并且在每个布线层中以一定间隔形成电源布线以执行,所述方法包括:提取一组相邻的宏单元 从布局数据; 在由布局数据表示的布局中包括的行区域中指定位于提取步骤中提取的构成相邻宏小区集合的宏小区之间的区域; 检测在所述指定步骤中指定的区域之上的投影区域中的特定布线层的电源布线,所述特定布线层高于由所述布局数据表示的布局的底层; 并且在检测步骤中输出没有检测到特定布线层的电源布线的区域。

    Apparatus and method for design support using layout positions of first and second terminals
    3.
    发明授权
    Apparatus and method for design support using layout positions of first and second terminals 有权
    使用第一和第二终端的布局位置的设计支持的装置和方法

    公开(公告)号:US08584069B2

    公开(公告)日:2013-11-12

    申请号:US12892481

    申请日:2010-09-28

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.

    摘要翻译: 由计算机执行的设计支持方法包括:从包括布置在多个方向上的宏单元的布局数据中检测单元中的第一终端的布局位置作为第一布局位置,所述第一终端布置在 第一个方向; 基于从所述第一取向到所述第二取向和所述第一布局位置的变化,计算布置在与所述第一取向不同的第二取向的第一端子的第二布局位置; 将第二布局位置与第一布局位置和布局数据相关联; 并输出关联结果。

    Designing supply wirings in semiconductor integrated circuit by detecting power supply wiring of specific wiring layer in projection area
    4.
    发明授权
    Designing supply wirings in semiconductor integrated circuit by detecting power supply wiring of specific wiring layer in projection area 有权
    通过检测投影区域中特定布线层的电源布线来设计半导体集成电路中的电源布线

    公开(公告)号:US08230376B2

    公开(公告)日:2012-07-24

    申请号:US12642044

    申请日:2009-12-18

    IPC分类号: G06F17/50

    摘要: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

    摘要翻译: 一种设计支持方法,用于使计算机使用布局数据来提供宏单元布置的布局,并且在每个布线层中以一定间隔形成电源布线以执行,所述方法包括:提取一组相邻的宏单元 从布局数据; 在由布局数据表示的布局中包括的行区域中指定位于提取步骤中提取的构成相邻宏小区集合的宏小区之间的区域; 检测在所述指定步骤中指定的区域之上的投影区域中的特定布线层的电源布线,所述特定布线层高于由所述布局数据表示的布局的底层; 并且在检测步骤中输出没有检测到特定布线层的电源布线的区域。

    Electronic device having connector
    6.
    发明授权
    Electronic device having connector 有权
    具有连接器的电子设备

    公开(公告)号:US08545238B2

    公开(公告)日:2013-10-01

    申请号:US13455779

    申请日:2012-04-25

    IPC分类号: H01R12/00

    摘要: An electronic device having a connector includes a case including an open end and a closed end, a circuit board housed in the case, an inner connector including a conduction terminal which is connected to the circuit board via a connecting portion, an outer connector including a contact face coming in contact with the circuit board, the outer connector being engaged with the open end, and a play preventing portion fixed in the case, and engaged with the circuit board by causing the circuit board to move from the open end to the closed end, wherein a position of the contact face is determined so that the circuit board is pressed by the contact face so as to cause the circuit board to be engaged with the play preventing portion, and the outer connector does not press the inner connector toward the closed end.

    摘要翻译: 具有连接器的电子设备包括:壳体,包括开口端和封闭端;容纳在壳体中的电路板;内部连接器,包括通过连接部连接到电路板的导电端子;外部连接器,包括: 与电路板接触的接触面,外部连接器与开口端接合;以及防止放置部,固定在壳体中,并且通过使电路板从开口端移动到封闭状态而与电路板接合 其中确定接触面的位置,使得电路板被接触面按压,以便使电路板与防止播放部分接合,并且外部连接器不将内部连接器朝向 封闭的

    SUPPORT APPARATUS AND DESIGN SUPPORT METHOD
    7.
    发明申请
    SUPPORT APPARATUS AND DESIGN SUPPORT METHOD 有权
    支持设备和设计支持方法

    公开(公告)号:US20110078646A1

    公开(公告)日:2011-03-31

    申请号:US12892481

    申请日:2010-09-28

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.

    摘要翻译: 由计算机执行的设计支持方法包括:从包括布置在多个方向上的宏单元的布局数据中检测单元中的第一终端的布局位置作为第一布局位置,所述第一终端布置在 第一个方向; 基于从所述第一取向到所述第二取向和所述第一布局位置的变化,计算布置在与所述第一取向不同的第二取向的第一端子的第二布局位置; 将第二布局位置与第一布局位置和布局数据相关联; 并输出关联结果。

    Method for designing wiring connecting section and semiconductor device
    8.
    发明授权
    Method for designing wiring connecting section and semiconductor device 失效
    布线连接部分和半导体器件的设计方法

    公开(公告)号:US07299443B2

    公开(公告)日:2007-11-20

    申请号:US11305224

    申请日:2005-12-19

    申请人: Kenji Kumagai

    发明人: Kenji Kumagai

    IPC分类号: G06F17/50

    摘要: First, an amount of a current flowing between a first wiring and a third wiring is estimated, and the number of stack vias required for connecting the first wiring and the third wiring is determined. Next, based on the number of stack vias, the number of virtual wirings for determining positions of the stack vias is determined. Thereafter, the virtual wirings are arranged in a forming region of the third wiring above the first wiring, for example, at an equal interval, and the stack vias are created in intersections of the first wiring and the virtual wirings. Thereafter, the virtual wirings are removed, and the third wiring is created. According to needs, a second wiring passing between the stack vias is created.

    摘要翻译: 首先,估计在第一布线和第三布线之间流动的电流量,并且确定连接第一布线和第三布线所需的堆叠通孔的数量。 接下来,基于堆叠通孔的数量,确定用于确定堆叠通孔的位置的虚拟布线的数量。 此后,虚拟布线例如以等间隔布置在第一布线上方的第三布线的形成区域中,并且在第一布线和虚拟布线的交叉处形成堆叠通孔。 此后,虚拟布线被去除,并且第三布线被创建。 根据需要,产生通过堆叠通孔之间的第二布线。

    Method for designing wiring connecting section and semiconductor device

    公开(公告)号:US20060097401A1

    公开(公告)日:2006-05-11

    申请号:US11305224

    申请日:2005-12-19

    申请人: Kenji Kumagai

    发明人: Kenji Kumagai

    IPC分类号: H01L23/48

    摘要: First, an amount of a current flowing between a first wiring and a third wiring is estimated, and the number of stack vias required for connecting the first wiring and the third wiring is determined. Next, based on the number of stack vias, the number of virtual wirings for determining positions of the stack vias is determined. Thereafter, the virtual wirings are arranged in a forming region of the third wiring above the first wiring, for example, at an equal interval, and the stack vias are created in intersections of the first wiring and the virtual wirings. Thereafter, the virtual wirings are removed, and the third wiring is created. According to needs, a second wiring passing between the stack vias is created.

    Method of designing semiconductor integrated circuit with accurate capacitance extraction
    10.
    发明授权
    Method of designing semiconductor integrated circuit with accurate capacitance extraction 失效
    具有精确电容提取的半导体集成电路设计方法

    公开(公告)号:US07032207B2

    公开(公告)日:2006-04-18

    申请号:US10762277

    申请日:2004-01-23

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068

    摘要: A semiconductor integrated circuit includes a block having a first border edge on which an external connection terminal is provided and a second border edge on which no external connection terminal is provided, a wiring prohibited area which extends a first distance from the first border edge and in which no wiring line running parallel to the first border edge exists, and a shielding line which is at a second distance from the second border edge and runs parallel to the second border edge.

    摘要翻译: 半导体集成电路包括具有第一边界的块,设置有外部连接端子的第一边界边缘和没有设置外部连接端子的第二边界边缘,从第一边界边缘延伸第一距离的布线禁止区域 不存在与第一边界边缘平行的布线,以及屏蔽线,该屏蔽线距离第二边框边缘第二距离并且平行于第二边框边缘延伸。