公开(公告)号：US20120260226A1

公开(公告)日：2012-10-11

申请号：US13528369

申请日：2012-06-20

Applicant: Kenji Kumagai ,  Jun Suda

Inventor： Kenji Kumagai ,  Jun Suda

IPC: G06F17/50

CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

Abstract translation: 一种设计支持方法，用于使计算机使用布局数据来提供宏单元布置的布局，并且在每个布线层中以一定间隔形成电源布线以执行，所述方法包括：提取一组相邻的宏单元 从布局数据; 在由布局数据表示的布局中包括的行区域中指定位于提取步骤中提取的构成相邻宏小区集合的宏小区之间的区域; 检测在所述指定步骤中指定的区域之上的投影区域中的特定布线层的电源布线，所述特定布线层高于由所述布局数据表示的布局的底层; 并且在检测步骤中输出没有检测到特定布线层的电源布线的区域。

公开(公告)号：US07622763B2

公开(公告)日：2009-11-24

申请号：US10565624

申请日：2004-07-28

Applicant: Jun Suda ,  Hiroyuki Matsunami

Inventor： Jun Suda ,  Hiroyuki Matsunami

IPC: H01L29/792

CPC classification number: H01L21/28158 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/511 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/802 ,  H01L29/803

Abstract: A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and a SiO2 layer formed thereon, and a gate electrode 15 formed on the insulation structure. Leakage current can be controlled while the state of interface with SiC is maintained in a good condition.

Abstract translation: 场效应晶体管包括SiC衬底1，形成在SiC衬底1的表面上的源极3a和漏极3b，绝缘结构，其包括与SiC表面接触形成的AlN层5， 层或更大，以及形成在其上的SiO 2层，以及形成在绝缘结构上的栅电极15。 可以控制漏电流，同时与SiC的界面状态保持良好状态。

公开(公告)号：US20090072243A1

公开(公告)日：2009-03-19

申请号：US11918733

申请日：2006-04-05

Applicant: Jun Suda ,  Tsunenobu Kimoto

Inventor： Jun Suda ,  Tsunenobu Kimoto

IPC: H01L29/24 ,  H01L21/30

CPC classification number: H01L21/26506 ,  G02F1/3551 ,  G02F1/3775 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02554 ,  H01L21/02658 ,  H01L21/76254 ,  H01L21/8213 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/16 ,  H01S5/021 ,  H01S5/026 ,  H01S5/3202 ,  H01S5/32341

Abstract: In the present invention, a technology for causing arbitrary polarity, crystal face and crystal orientation to exist mixedly in a plane on the surface of a SiC substrate, and for forming a SiC layer or a group III-nitride or group II-oxide layer on the surface, is provided. A first SiC substrate 41 having (0001) face and a second SiC substrate 44 having (000-1) face are prepared. An oxide film 43 is formed on the surfaces of the SiC substrates 41 and 44 by subjecting them to an oxidation treatment, and then the two SiC substrates are fusion-bonded so that the rear surface of the second SiC substrate and the surface of the first SiC substrate are brought into contact with each other. Subsequently, a part corresponding to the second SiC substrate 44 is made thin (44a). Subsequently, a thin layer 44a of the second SiC substrate is removed in accordance with required periodic reversal to be processed in stripes by using a lithography technology and reactive ion etching technology. This enables a substrate to be produced, where the (0001) face and the (000-1) face of SiC appear alternately on the surface (a region denoted by reference numeral 441 and a region denoted by 44b/43a). On the substrate thus produced, an AlGaN layer 45a to be a first cladding layer, a GaN layer 46a to be an optical guide layer, and an AlGaN layer 45c to be a second cladding layer, are grown. The group III-nitrides grow while inheriting the face orientation of SiC exposed on the surface and thereby a structure where crystal axes are spatially-periodically reversed can be attained. In other words, a second laminated structure 45a/46b/47a is formed on the first laminated structure 43a/44b, and a third laminated structure 45b/46b/47b is formed on a region where the first laminated structure 43a/44b is not formed. Finally, a stripe structure for realizing light confinement in the lateral direction, i.e. the in-plane direction of the substrate, is formed by using a known processing technology including lithography and reactive ion etching, thus completing a non-linear optical element.

公开(公告)号：US20060180077A1

公开(公告)日：2006-08-17

申请号：US10549683

申请日：2004-03-18

Applicant: Jun Suda ,  Hiroyuki Matsunami ,  Norio Onojima

Inventor： Jun Suda ,  Hiroyuki Matsunami ,  Norio Onojima

IPC: C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: C30B29/406 ,  C30B23/002 ,  C30B29/403 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02631 ,  H01L21/02658 ,  H01L21/02661

Abstract: SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrate 1 is rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrate 1 is then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrate 1 is etched so as to form a clean SiC surface 3 on the substrate surface. The SiC substrate 1 is then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10−6 to 10−8 Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beam 5 at time t1 at temperature of 800° C. or lower and performing a heating treatment at 800° C. or higher is repeated at least once. The temperature is then set to the growth temperature of an AlN film, and the SiC substrate surface 3 is initially irradiated with —Al atoms 8a in ultrahigh vacuum state, followed by the feeding of N atoms 8b.

Abstract translation: SiC是非常稳定的物质，在传统的III族氮化物晶体生长装置中难以控制SiC表面适合于晶体生长的状态。 这个问题解决如下。 通过在HCl气体气氛中进行加热处理，将SiC衬底1的表面制成台阶平台结构。 然后依次用王水，盐酸和氢氟酸处理SiC衬底1的表面。 蚀刻形成在SiC衬底1的表面上的少量氧化硅膜，从而在衬底表面上形成清洁的SiC表面3。 然后将SiC基板1安装在高真空装置中，并且内部的压力保持在超高真空（例如10 -6至10 -8 Pa）。 在超高真空状态下，在800℃以下的温度下，在时刻t 1的Ga原子束5照射表面，进行800℃以上的加热处理，至少重复一次。 然后将温度设定为AlN膜的生长温度，并且首先用超高真空状态的-Al原子8a照射SiC衬底表面3，然后馈送N原子8b。

公开(公告)号：US07625447B2

公开(公告)日：2009-12-01

申请号：US10549683

申请日：2004-03-18

Applicant: Jun Suda ,  Hiroyuki Matsunami ,  Norio Onojima

Inventor： Jun Suda ,  Hiroyuki Matsunami ,  Norio Onojima

IPC: C30B23/00

CPC classification number: C30B29/406 ,  C30B23/002 ,  C30B29/403 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02631 ,  H01L21/02658 ,  H01L21/02661

Abstract: SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrate 1 is rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrate 1 is then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrate 1 is etched so as to form a clean SiC surface 3 on the substrate surface. The SiC substrate 1 is then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10−6 to 10−8 Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beam 5 at time t1 at temperature of 800° C. or lower and performing a heating treatment at 800° C. or higher is repeated at least once. The temperature is then set to the growth temperature of an AlN film, and the SiC substrate surface 3 is initially irradiated with Al atoms 8a in ultrahigh vacuum state, followed by the feeding of N atoms 8b.

Abstract translation: SiC是非常稳定的物质，在传统的III族氮化物晶体生长装置中难以控制SiC表面适合于晶体生长的状态。 这个问题解决如下。 通过在HCl气体气氛中进行加热处理，将SiC衬底1的表面制成台阶平台结构。 然后依次用王水，盐酸和氢氟酸处理SiC衬底1的表面。 蚀刻形成在SiC衬底1的表面上的少量氧化硅膜，从而在衬底表面上形成清洁的SiC表面3。 然后将SiC基板1安装在高真空装置中，并且内部的压力保持在超高真空（例如10-6至10-8Pa）。 在超高真空状态下，在800℃以下的温度下在时刻t1的Ga原子束5照射表面，进行800℃以上的加热处理的工序至少重复一次。 然后将温度设定为AlN膜的生长温度，并且首先用超高真空状态的Al原子8a照射SiC衬底表面3，然后馈送N原子8b。

公开(公告)号：US20060102924A1

公开(公告)日：2006-05-18

申请号：US10525753

申请日：2003-08-21

Applicant: Shigeki Otani ,  Hiroyuki Kinoshita ,  Hiroyuki Matsunami ,  Jun Suda ,  Hiroshi Amano ,  Isamu Akasaki ,  Satoshi Kamiyama

Inventor： Shigeki Otani ,  Hiroyuki Kinoshita ,  Hiroyuki Matsunami ,  Jun Suda ,  Hiroshi Amano ,  Isamu Akasaki ,  Satoshi Kamiyama

IPC: H01L33/00

CPC classification number: H01L31/0264 ,  C30B29/10 ,  C30B33/00 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/24 ,  H01S5/0213 ,  H01S5/0218 ,  H01S5/32341

Abstract: Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate 1 of diboride XB2 (where X is either Zr or Ti) which is facially oriented in a (0001) plane 2 and has a thickness of 0.1 mm or less. The substrate 1 is permitted cleaving and splitting along a (10-10) plane 4 with ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.

Abstract translation: 公开了具有与氮化物化合物半导体相同的解理面并具有导电性的二硼化物单晶基板; 半导体激光二极管和使用这种衬底的半导体器件及其制造方法，其中衬底是面向取向的二硼化物XB 2 N（其中X是Zr或Ti）的单晶衬底1 在（0001）面2中，具有0.1mm以下的厚度。 允许衬底1容易地沿着（10-10）平面4进行切割和分割。 使用该基板形成氮化物化合物的半导体激光二极管，可以实现垂直结构装置。 具有最小损耗的半导体激光二极管的谐振平面可以通过在与（10-10）平面平行的方向上分割器件来制造。 还实现了消除切割余量的制造方法。

公开(公告)号：US20050066885A1

公开(公告)日：2005-03-31

申请号：US10500002

申请日：2002-12-26

Applicant: Satoshi Kamiyama ,  Hiroshi Amano ,  Isamu Akasaki ,  Shigeki Ohtani ,  Jun Suda

Inventor： Satoshi Kamiyama ,  Hiroshi Amano ,  Isamu Akasaki ,  Shigeki Ohtani ,  Jun Suda

IPC: C30B29/38 ,  C30B25/02 ,  C30B25/18 ,  H01L21/20 ,  H01L21/205 ,  H01L33/12 ,  H01L33/32 ,  H01S5/323 ,  B32B9/00 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: C30B25/02 ,  C30B25/18 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/007

Abstract: Disclosed are a group III-nitride semiconductor substrate and a production method therefor. A group III-nitride semiconductor substrate having an element-forming surface with a dislocation density of 107 cm−2 or less in its entirely is formed only two steps. In a first step, a AlGaN-based low-temperature buffer layer is formed on a ZrB2 single crystal base having a defect density of 107 cm−2 or less, at a base temperature allowing the low-temperature buffer layer to be grown or deposited on the ZrB2 single crystal base substantially without creation of any Zr—B—N amorphous nitrided layer. Subsequently, in a second step, an AlGaN-based single crystal film is grown directly on the low-temperature buffer layer. The present invention can fully bring out the properties of the ZrB2 single crystal base having a high potential as a base material capable of lattice marching with group III-nitride semiconductors, so as to achieve a high-quality AlGaN semiconductor layer with an element-forming surface having a low dislocation density, through a fully simplified process.

Abstract translation: 公开了III族氮化物半导体衬底及其制造方法。 具有位错密度为10 -7 cm -2以下的元素形成表面的III族氮化物半导体衬底完全仅形成两个步骤。 在第一步骤中，在基底温度下，在缺陷密度为10 -7 cm -2以下的ZrB2单晶基底上形成AlGaN系低温缓冲层，使得低温缓冲层 在ZrB2单晶基底上生长或沉积，基本上不产生任何Zr-BN无定形氮化层。 随后，在第二步骤中，直接在低温缓冲层上生长AlGaN基单晶膜。 本发明可以充分发挥具有高电位的ZrB2单晶基体作为能够与III族氮化物半导体进行晶格游离的基体材料的性能，从而获得具有元素形成的高质量的AlGaN半导体层 表面具有低位错密度，通过完全简化的过程。

公开(公告)号：US08347253B2

公开(公告)日：2013-01-01

申请号：US13528369

申请日：2012-06-20

Applicant: Kenji Kumagai ,  Jun Suda

Inventor： Kenji Kumagai ,  Jun Suda

IPC: G06F17/50

CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

Abstract translation: 一种设计支持方法，用于使计算机使用布局数据来提供宏单元布置的布局，并且在每个布线层中以一定间隔形成电源布线以执行，所述方法包括：提取一组相邻的宏单元 从布局数据; 在由布局数据表示的布局中包括的行区域中指定位于提取步骤中提取的构成相邻宏小区集合的宏小区之间的区域; 检测在所述指定步骤中指定的区域之上的投影区域中的特定布线层的电源布线，所述特定布线层高于由布局数据表示的布局的底层; 并且在检测步骤中输出没有检测到特定布线层的电源布线的区域。

公开(公告)号：US07297989B2

公开(公告)日：2007-11-20

申请号：US10525753

申请日：2003-08-21

Applicant: Shigeki Otani ,  Hiroyuki Kinoshita ,  Hiroyuki Matsunami ,  Jun Suda ,  Hiroshi Amano ,  Isamu Akasaki ,  Satoshi Kamiyama

Inventor： Shigeki Otani ,  Hiroyuki Kinoshita ,  Hiroyuki Matsunami ,  Jun Suda ,  Hiroshi Amano ,  Isamu Akasaki ,  Satoshi Kamiyama

IPC: H01L33/00

CPC classification number: H01L31/0264 ,  C30B29/10 ,  C30B33/00 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/24 ,  H01S5/0213 ,  H01S5/0218 ,  H01S5/32341

Abstract: Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate 1 of diboride XB2 (where X is either Zr or Ti) which is facially oriented in a (0001) plane 2 and has a thickness of 0.1 mm or less. The substrate 1 is permitted cleaving and splitting along a (10-10) plane 4 with ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.

Abstract translation: 公开了具有与氮化物化合物半导体相同的解理面并具有导电性的二硼化物单晶基板; 半导体激光二极管和使用这种衬底的半导体器件及其制造方法，其中衬底是面向取向的二硼化物XB 2 N（其中X是Zr或Ti）的单晶衬底1 在（0001）面2中，具有0.1mm以下的厚度。 允许衬底1容易地沿着（10-10）平面4进行切割和分割。 使用该基板形成氮化物化合物的半导体激光二极管，可以实现垂直结构装置。 具有最小损耗的半导体激光二极管的谐振平面可以通过在与（10-10）平面平行的方向上分割器件来制造。 还实现了消除切割余量的制造方法。

公开(公告)号：US20100169851A1

公开(公告)日：2010-07-01

申请号：US12642044

申请日：2009-12-18

Applicant: Kenji Kumagai ,  Jun Suda

Inventor： Kenji Kumagai ,  Jun Suda

IPC: G06F17/50

CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

Abstract translation: 一种设计支持方法，用于使计算机使用布局数据来提供宏单元布置的布局，并且在每个布线层中以一定间隔形成电源布线以执行，所述方法包括：提取一组相邻的宏单元 从布局数据; 在由布局数据表示的布局中包括的行区域中指定位于提取步骤中提取的构成相邻宏小区集合的宏小区之间的区域; 检测在所述指定步骤中指定的区域之上的投影区域中的特定布线层的电源布线，所述特定布线层高于由所述布局数据表示的布局的底层; 并且在检测步骤中输出没有检测到特定布线层的电源布线的区域。