公开(公告)号：US20120064687A1

公开(公告)日：2012-03-15

申请号：US13227622

申请日：2011-09-08

申请人： Yoshiyuki Kondo ,  Kimitoshi Okano ,  Shigeru Kawanaka

发明人： Yoshiyuki Kondo ,  Kimitoshi Okano ,  Shigeru Kawanaka

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823437 ,  H01L29/1083 ,  H01L29/66545

摘要： According to one embodiment, a method of manufacturing a semiconductor device includes: forming a gate electrode on a substrate via a gate dielectric film; forming a first insulating film on the gate electrode, the first insulating film having a first groove in a central region of the first insulating film; and forming a halo region in the substrate below a side surface of the gate electrode, by injecting an impurity into the substrate through the first insulating film.

摘要翻译： 根据一个实施例，制造半导体器件的方法包括：通过栅极电介质膜在衬底上形成栅电极; 在所述栅电极上形成第一绝缘膜，所述第一绝缘膜在所述第一绝缘膜的中心区域具有第一槽; 以及通过所述第一绝缘膜将杂质注入到所述衬底中，在所述栅电极的侧表面下方的所述衬底中形成晕圈。

公开(公告)号：US20130134504A1

公开(公告)日：2013-05-30

申请号：US13600982

申请日：2012-08-31

申请人： Yoshiyuki Kondo ,  Shigeru Kawanaka

发明人： Yoshiyuki Kondo ,  Shigeru Kawanaka

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7391

摘要： In one embodiment, a semiconductor device includes a substrate including a trench, and a gate electrode disposed at a position adjacent to the trench on the substrate, the gate electrode having a first side surface located on an opposite side of the trench, and a second side surface located on the same side as the trench. The device further includes a first sidewall insulator disposed on the first side surface, and a second sidewall insulator disposed on the second side surface and a side surface of the trench. The device further includes a source region of a first conductivity type disposed in the substrate on the same side as the first sidewall insulator with respect to the first side surface, and a drain region of a second conductivity type disposed in the substrate on the same side as the second sidewall insulator with respect to the second side surface.

摘要翻译： 在一个实施例中，半导体器件包括包括沟槽的衬底和设置在与衬底上的沟槽相邻的位置处的栅电极，栅电极具有位于沟槽相对侧上的第一侧表面， 侧表面位于与沟槽相同的一侧。 该装置还包括设置在第一侧表面上的第一侧壁绝缘体和设置在第二侧表面上的第二侧壁绝缘体和沟槽的侧表面。 该器件还包括：第一导电类型的源极区域，设置在与第一侧壁绝缘体相同的第一侧表面的同一侧的衬底中;以及布置在同一侧的衬底中的第二导电类型的漏极区域 作为第二侧壁绝缘体相对于第二侧表面。

公开(公告)号：US20120074476A1

公开(公告)日：2012-03-29

申请号：US13230077

申请日：2011-09-12

申请人： Yoshiyuki Kondo ,  Shigeru Kawanaka

发明人： Yoshiyuki Kondo ,  Shigeru Kawanaka

IPC分类号： H01L27/088

CPC分类号： H01L27/0605 ,  H01L27/088 ,  H01L29/66984

摘要： In accordance with an embodiment, an integrated circuit includes a circuit in which first and second spin transistors are connected in series. The first spin transistor has a first node and a second node that are equal to each other in magnetization direction. The second spin transistor has a third node and a fourth node that are opposite to each other in magnetization direction. The second node and the fourth node are electrically connected to each other.

摘要翻译： 根据实施例，集成电路包括其中第一和第二自旋晶体管串联连接的电路。 第一自旋晶体管具有在磁化方向上彼此相等的第一节点和第二节点。 第二自旋晶体管具有在磁化方向上彼此相对的第三节点和第四节点。 第二节点和第四节点彼此电连接。

公开(公告)号：US20120068235A1

公开(公告)日：2012-03-22

申请号：US13230066

申请日：2011-09-12

申请人： Yoshiyuki Kondo ,  Shigeru Kawanaka

发明人： Yoshiyuki Kondo ,  Shigeru Kawanaka

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L27/0605 ,  H01L29/66984

摘要： In accordance with an embodiment, an integrated circuit includes a first spin transistor and a second spin transistor. The first spin transistor has a first channel length. The first spin transistor includes a first node and a second node apart from the first node The second spin transistor is connected to the first transistor in series and has a second channel length different from the first channel length. The second spin transistor includes a third node and a fourth node apart from the third node The second node and the fourth node are electrically connected to each other.

摘要翻译： 根据实施例，集成电路包括第一自旋晶体管和第二自旋晶体管。 第一自旋晶体管具有第一通道长度。 第一自旋晶体管包括第一节点和离开第一节点的第二节点。第二自旋晶体管串联连接到第一晶体管，并具有不同于第一沟道长度的第二沟道长度。 第二自旋晶体管包括第三节点和离开第三节点的第四节点。第二节点和第四节点彼此电连接。

公开(公告)号：US09059235B2

公开(公告)日：2015-06-16

申请号：US13600982

申请日：2012-08-31

申请人： Yoshiyuki Kondo ,  Shigeru Kawanaka

发明人： Yoshiyuki Kondo ,  Shigeru Kawanaka

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/739

CPC分类号： H01L29/7391

摘要： In one embodiment, a semiconductor device includes a substrate including a trench, and a gate electrode disposed at a position adjacent to the trench on the substrate, the gate electrode having a first side surface located on an opposite side of the trench, and a second side surface located on the same side as the trench. The device further includes a first sidewall insulator disposed on the first side surface, and a second sidewall insulator disposed on the second side surface and a side surface of the trench. The device further includes a source region of a first conductivity type disposed in the substrate on the same side as the first sidewall insulator with respect to the first side surface, and a drain region of a second conductivity type disposed in the substrate on the same side as the second sidewall insulator with respect to the second side surface.

摘要翻译： 在一个实施例中，半导体器件包括包括沟槽的衬底和设置在与衬底上的沟槽相邻的位置处的栅电极，栅电极具有位于沟槽相对侧上的第一侧表面， 侧表面位于与沟槽相同的一侧。 该装置还包括设置在第一侧表面上的第一侧壁绝缘体和设置在第二侧表面上的第二侧壁绝缘体和沟槽的侧表面。 该器件还包括：第一导电类型的源极区域，设置在与第一侧壁绝缘体相同的第一侧表面的同一侧的衬底中;以及布置在同一侧的衬底中的第二导电类型的漏极区域 作为第二侧壁绝缘体相对于第二侧表面。

公开(公告)号：US20110284938A1

公开(公告)日：2011-11-24

申请号：US13053399

申请日：2011-03-22

申请人： Shigeru Kawanaka ,  Kanna Adachi ,  Yoshiyuki Kondo

发明人： Shigeru Kawanaka ,  Kanna Adachi ,  Yoshiyuki Kondo

IPC分类号： H01L29/82

CPC分类号： H01L29/66984 ,  G11C11/16 ,  H01F10/1936

摘要： A spin transistor according to an embodiment includes: a first magnetic region supplying a first polarized signal polarized in a first magnetization direction in accordance with a first input signal; a second magnetic region supplying a second polarized signal polarized in a second magnetization direction opposite from the first magnetization direction in accordance with a second input signal, the second input signal being different from the first input signal; and a third magnetic region outputting the first polarized signal supplied from the first magnetic region in accordance with a third input signal, and outputting the second polarized signal supplied from the second magnetic region in accordance with a fourth input signal different from the third input signal.

摘要翻译： 根据实施例的自旋晶体管包括：第一磁区，根据第一输入信号提供沿第一磁化方向偏振的第一偏振信号; 第二磁区，根据第二输入信号，提供沿与第一磁化方向相反的第二磁化方向偏振的第二极化信号，第二输入信号不同于第一输入信号; 以及第三磁区，根据第三输入信号输出从第一磁区提供的第一极化信号，并根据与第三输入信号不同的第四输入信号输出从第二磁区提供的第二极化信号。

公开(公告)号：US08405159B2

公开(公告)日：2013-03-26

申请号：US13234536

申请日：2011-09-16

申请人： Kanna Adachi ,  Shigeru Kawanaka ,  Satoshi Inaba

发明人： Kanna Adachi ,  Shigeru Kawanaka ,  Satoshi Inaba

IPC分类号： H01L27/088

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L29/4238

摘要： In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors.

摘要翻译： 根据实施例，半导体器件在衬底上包括SRAM单元。 SRAM单元包括：具有n型源极区域和p型漏极区域的第一和第二负载晶体管，每个具有p型源极区域和n型漏极区域的第一和第二驱动器晶体管，以及第一和第二负极晶体管， 第二传输晶体管，每个具有n型源极区和n型漏极区。 第一和第二负载晶体管的n型源极区域，第一和第二驱动晶体管的n型漏极区域以及第一和第二转移晶体管的n型源极区域和n型漏极区域是 位于除了存在于第一和第二负载晶体管的任何两个p型漏极区域之间的区域以及第一和第二驱动器晶体管的p型源极区域之外的区域中。

公开(公告)号：US20110227044A1

公开(公告)日：2011-09-22

申请号：US13046940

申请日：2011-03-14

申请人： Shigeru Kawanaka ,  Kanna Adachi ,  Toshitaka Miyata ,  Hideji Tsujii

发明人： Shigeru Kawanaka ,  Kanna Adachi ,  Toshitaka Miyata ,  Hideji Tsujii

IPC分类号： H01L29/08 ,  B82Y99/00

CPC分类号： H01L29/78684 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/778 ,  H01L29/7839

摘要： In one embodiment, a transistor includes: a substrate; a source electrode formed on the substrate; a drain electrode formed on the substrate; a graphene film formed between the source electrode and the drain electrode, the graphene film having a semiconductor region including a source side end and a conductor region including a drain side end, a width of the source side end of the graphene film in a channel width direction being narrower than a width of the drain side end of the graphene film in the channel width direction; and a gate electrode formed via a gate insulating film on the semiconductor region of the graphene film and the conductor region of the graphene film. The source electrode is connected to the source side end of the graphene film with a Schottky contact, and the drain electrode is connected to the drain side end of the graphene film with an ohmic contact.

摘要翻译： 在一个实施例中，晶体管包括：衬底; 形成在所述基板上的源电极; 形成在所述基板上的漏电极; 形成在源电极和漏电极之间的石墨烯膜，所述石墨烯膜具有包括源极侧端部和包括漏极侧端部的导体区域的半导体区域，所述石墨烯膜的源极侧端部的宽度在沟道宽度 方向比通道宽度方向上的石墨烯膜的漏极侧端部的宽度窄; 以及在石墨烯膜的半导体区域和石墨烯膜的导体区域上经由栅极绝缘膜形成的栅电极。 源电极以肖特基接触连接到石墨烯膜的源侧端，并且漏电极以欧姆接触连接到石墨烯膜的漏极侧端。

公开(公告)号：US20060157738A1

公开(公告)日：2006-07-20

申请号：US11369041

申请日：2006-03-07

申请人： Shigeru Kawanaka

发明人： Shigeru Kawanaka

IPC分类号： H01L27/10

CPC分类号： H01L21/84 ,  G11C11/405 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/7841

摘要： According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each memory cell being connected to a bit line and the other side of each memory cell being supplied with a reference potential, and according to another aspect of the present invention, a semiconductor memory device manufacturing method includes: forming an oxide layer and a silicon active layer on a semiconductor substrate; forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer; forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it; injecting predetermined ions into a region for forming a diffusion layer in, using said gate electrodes as an ion injection mask; forming said paired transistors by activating the injected ions through a heat process; and forming a first gate line connected to the gate electrode of one of said paired transistors and a second gate line connected to the gate electrode of the other of said paired transistors.

公开(公告)号：US06576956B2

公开(公告)日：2003-06-10

申请号：US09902700

申请日：2001-07-12

申请人： Shigeru Kawanaka

发明人： Shigeru Kawanaka

IPC分类号： H01L2701

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H03K19/0948

摘要： A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.