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    Three-dimensional packaging of semiconductor device chips
    1.
    发明授权
    Three-dimensional packaging of semiconductor device chips 失效
    半导体器件芯片的三维封装

    公开(公告)号：US4894706A

    公开(公告)日：1990-01-16

    申请号：US919001

    申请日：1986-10-09

    申请人： Yoshiyuki Sato ,  Kazuhide Kiuchi ,  Junji Watanabe ,  Kunio Koyabu ,  Masanobu Oohata ,  Katsuhiko Aoki

    发明人： Yoshiyuki Sato ,  Kazuhide Kiuchi ,  Junji Watanabe ,  Kunio Koyabu ,  Masanobu Oohata ,  Katsuhiko Aoki

    IPC分类号： H01L25/065 ,  H01L25/10

    CPC分类号： H01L25/0657 ,  H01L25/105 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/0002 ,  Y10T29/49133

    摘要： A chip carrying member (1) such as a film carrier carrying a chip (10) and elastic spacers (2, 3) are stacked to form an elementary unit with adjusting its thickness. By using an aligning aperture (12) of a thin sheet (1), a plurality of the elementary units are stacked to form a laminated structure. From a side surface of the laminated structure, leads (13) are extended to be connected to a wiring board (241), or after the leads (13) are buried in an insulator (8), the leads (13) and insulator (8) are abraded to form a coplanar surface and then a wiring layer (82) for interconnecting is formed on the abraded surface. A usual chip can be mounted on the chip carrying member (1) without any work with a high accuracy in alignment of the lamination and furthermore with a high accuracy in a lamination pitch of the chip carrying member (1), so that the leads (13) of the chip (10) can be wired precisely and finely. A low cost and high density three-dimensional packaging structure can be realized.

    摘要翻译： PCT No.PCT / JP86 / 00065 Sec。 371日期1986年10月9日第 102（e）1986年10月9日PCT PCT日期为1986年2月14日。堆叠载置有芯片（10）和弹性间隔物（2,3）的载片（1），形成基片 单位调整其厚度。 通过使用薄片（1）的对准孔（12），堆叠多个基本单元以形成层压结构。 从叠层结构的侧面，引线（13）延伸以连接到布线板（241），或者在引线（13）埋在绝缘体（8）中之后，引线（13）和绝缘体 8）磨损以形成共面，然后在磨损表面上形成用于互连的布线层（82）。 通常的芯片可以安装在芯片承载构件（1）上，而不需要高度准确地对齐层压的工作，并且还具有芯片承载构件（1）的层压间距的高精度，使得引线 可以精确地精细地布线芯片（10）13。 可以实现低成本和高密度三维包装结构。

    Method of manufacturing semiconductor device
    2.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US5213991A

    公开(公告)日：1993-05-25

    申请号：US856801

    申请日：1992-03-24

    申请人： Hiroshi Inokawa ,  Toshio Kobayashi ,  Kazuhide Kiuchi

    发明人： Hiroshi Inokawa ,  Toshio Kobayashi ,  Kazuhide Kiuchi

    IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/768 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

    CPC分类号： H01L29/66651 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76877 ,  H01L29/1033 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/78

    摘要： In a method of making a MOSFET-type semiconductor device of this invention, a surface of a semiconductor substrate is covered in a predetermined pattern with an insulating layer comprising a silicon-nitride-containing film or with an insulating layer whose top surface and side surfaces bear a silicon-nitride-containing film, thereby forming on the semiconductor substrate a recess region at which the semiconductor substrate is exposed. An epitaxial silicon film and polycrystalline silicon film are formed simultaneously on the exposed semiconductor substrate and on the insulating film, respectively. A whole channel region and a part of source and drain diffused-layer regions are formed in the epitaxial silicon film, and source and drain diffused-layer regions are formed in the polycrystalline silicon film. A gate electrode of this MOSFET-type semiconductor device may be formed at the recess region by a self-align method.

    摘要翻译： 在制造本发明的MOSFET型半导体器件的方法中，半导体衬底的表面以包含含氮化硅的膜的绝缘层或具有绝缘层的预定图案被覆盖，所述绝缘层的顶表面和侧表面 承载含氮化硅的膜，从而在半导体衬底上形成露出半导体衬底的凹部区域。 外延硅膜和多晶硅膜分别同时形成在暴露的半导体衬底和绝缘膜上。 在外延硅膜中形成整个沟道区域和一部分源极和漏极扩散层区域，并且在多晶硅膜中形成源极和漏极扩散层区域。 该MOSFET型半导体器件的栅极可以通过自对准方法在凹陷区域形成。