公开(公告)号：US20120009767A1

公开(公告)日：2012-01-12

申请号：US13236000

申请日：2011-09-19

申请人： Young-Chul JANG ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

发明人： Young-Chul JANG ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

IPC分类号： H01L21/20

CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

公开(公告)号：US20100012997A1

公开(公告)日：2010-01-21

申请号：US12499980

申请日：2009-07-09

申请人： Young-Chul JANG ,  Han-Soo KIM ,  Jae-Hun JEONG ,  Soon-Moon JUNG

发明人： Young-Chul JANG ,  Han-Soo KIM ,  Jae-Hun JEONG ,  Soon-Moon JUNG

IPC分类号： H01L29/788

CPC分类号： H01L27/11578 ,  H01L27/11524 ,  H01L27/11551 ,  H02J2007/0049

摘要： Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.

摘要翻译： 公开了闪存装置和操作方法。 闪速存储器件包括底部存储单元阵列和设置在底部存储单元阵列上的顶部存储器单元阵列。 底部存储单元阵列包括底部半导体层，底部阱以及多个底部存储单元单元。 顶部存储单元阵列包括顶部半导体层，顶部阱以及多个顶部存储单元。 井顶偏置线设置在顶部存储单元阵列上，并且包括底部阱偏置线和顶部阱偏置线。底部阱偏置线电连接到底部阱，并且顶部阱偏置线电连接到 顶好

公开(公告)号：US20090203180A1

公开(公告)日：2009-08-13

申请号：US12423404

申请日：2009-04-14

申请人： Young-Chul JANG

发明人： Young-Chul JANG

IPC分类号： H01L21/762

CPC分类号： H01L29/7851 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66818 ,  H01L29/7854

摘要： A MOS transistor that has a protruding portion with a favorable vertical profile and a protruded-shape channel that requires no additional photolithography process, and a method of fabricating the same are provided. A first mask that defines an isolation region of a substrate is overall etched to form a second mask with a smaller width than the first mask. Then, the substrate is etched to a predetermined depth while using the second mask as an etch mask, thereby forming the protruding portion. Without performing a photolithography process, the protruding portion has a favorable profile and the protruding height of an isolation layer is adjusted to be capable of appropriately performing ion implantation upon the protruding portion.

摘要翻译： 具有具有良好垂直剖面的突出部分和不需要附加光刻工艺的突出形状的沟道的MOS晶体管及其制造方法。 限定衬底的隔离区域的第一掩模被总体蚀刻以形成具有比第一掩模更小的宽度的第二掩模。 然后，在使用第二掩模作为蚀刻掩模的同时将基板蚀刻到预定深度，从而形成突出部分。 在不进行光刻处理的情况下，突出部具有良好的轮廓，并且隔离层的突出高度被调整为能够适当地进行离子注入在突出部上。