公开(公告)号：US5638321A

公开(公告)日：1997-06-10

申请号：US631977

申请日：1996-04-15

申请人： Young-man Lee ,  Chan-dong Cho ,  Won-woo Rhee ,  Byung-jun Kim ,  Eun-sang Park

发明人： Young-man Lee ,  Chan-dong Cho ,  Won-woo Rhee ,  Byung-jun Kim ,  Eun-sang Park

IPC分类号： H04N5/76 ,  G07F7/10 ,  G11C16/10 ,  G11C11/34

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/35765 ,  G11C16/102

摘要： A recorder for an IC memory card (37) using a NAND-type flash memory assigns a single address to both audio and video source data, matching a structure of the NAND-type flash memory. Consequently, the audio and video source data may be recorded with a single address. The recorder includes a first memory (32) for accessing video data in units of a basic region of one page in the NAND-type flash memory, and a second memory (33) for accessing audio data in units of a dummy region of one page in the NAND-type flash memory. A first latch (34) and a second latch (35) match the timing of the video data and the audio data, respectively, accessible from the memories (32, 33). A page memory (36) records the video data output via the first latch (34) and then records the audio data output via the second latch (35) sequentially to thereby store data of a whole one-page unit. A controller (31) is provided for accessing the video data in units of a basic region from the first memory (32), accessing the audio data in units of a dummy region from the second memory (33), and enabling the first and second latches (34, 35) to be latched in order to sequentially record the audio and video data together in the page memory (36). Then a single address is assigned, in the IC memory card, to a one-page unit data stored in the page memory (36) to record the one-page unit of data, containing both audio and video information.

摘要翻译： 使用NAND型闪速存储器的IC存储卡（37）的记录器为NAND型闪速存储器的结构匹配音频和视频源数据的单个地址。 因此，音频和视频源数据可以用单个地址记录。 记录器包括用于以NAND型闪速存储器中的一页的基本区域为单位访问视频数据的第一存储器（32）和用于以一页的虚拟区域为单位访问音频数据的第二存储器（33） 在NAND型闪存中。 第一锁存器（34）和第二锁存器（35）分别匹配从存储器（32,33）可访问的视频数据和音频数据的定时。 页存储器（36）记录经由第一锁存器（34）输出的视频数据，然后依次经由第二锁存器（35）输出的音频数据记录，从而存储整个一页单元的数据。 提供控制器（31），用于以来自第一存储器（32）的基本区域为单位访问视频数据，以来自第二存储器（33）的虚拟区域为单位访问音频数据，以及使第一和第二 锁存器（34,35）被锁存以便将页面存储器（36）中的音频和视频数据顺序地记录在一起。 然后，在IC存储卡中分配单个地址到存储在页面存储器（36）中的一页单元数据，以记录包含音频和视频信息的一页数据单元。

公开(公告)号：US5805715A

公开(公告)日：1998-09-08

申请号：US267498

申请日：1994-06-29

申请人： Won-woo Rhee

发明人： Won-woo Rhee

IPC分类号： H04R3/04 ,  H04B1/12

CPC分类号： H04R3/04

摘要： A distortion compensation apparatus heightens resolution of a low frequency domain among the audible frequency band, and relatively lowers the resolution in the higher frequency domain. By performing the band division using a Bark scale, filter coefficients are determined. The acoustic signal of the entire audible frequency band which does not pass a low-pass filter is distortion-compensated by a first filter portion. The acoustic signal of the divided band, which is obtained by passing the low-pass filter, is filtered so as to remove a portion of the distortion which is not compensated by signal distortion compensation of the entire audible frequency band by means of a second filter portion. Then, the filtered signal is added to the distortion-compensated acoustic signal of the entire audible frequency band. The remaining signal distortion portion in the distortion compensated acoustic signal by the first filter portion is removed by the signal output from the second filter. Thus, the number of the taps can be reduced and the distortion of the acoustic signal which human cannot recognize with his ear can be compensated.

摘要翻译： 失真补偿装置提高了可听频带中低频域的分辨率，并且相对降低了较高频域中的分辨率。 通过使用Bark标度进行带分割，确定滤波器系数。 不通过低通滤波器的整个可听频带的声信号由第一滤波器部分进行失真补偿。 对通过低通滤波器获得的分频带的声信号进行滤波，以便通过第二滤波器去除未被整个可听频带的信号失真补偿补偿的失真部分 一部分。 然后，滤波后的信号被加到整个可听频带的失真补偿声信号中。 第一滤波器部分的失真补偿声信号中的剩余信号失真部分被从第二滤波器输出的信号去除。 因此，可以减少抽头的数量，并且可以补偿人类用他的耳朵不能识别的声信号的失真。

公开(公告)号：US5608673A

公开(公告)日：1997-03-04

申请号：US507689

申请日：1995-07-25

申请人： Won-woo Rhee

发明人： Won-woo Rhee

IPC分类号： G11C17/00 ,  G06K19/07 ,  G11C5/00 ,  G11C16/02 ,  G11C16/08 ,  G11C11/34

CPC分类号： G11C16/08

摘要： A NAND-type flash memory integrated circuit card is composed of an input and output bus having first lines for a plurality of NAND-type flash memory components having first and second groups, first lines for zone address data, instruction data, address data and information data, and second lines for the information data only, a first buffer for transmitting the data between the first lines and the NAND-type flash memory components of the first group, a second buffer for transmitting the data between the first lines and the NAND-type flash memory components of the second group, a third buffer for transmitting the data between the second lines and the NAND-type flash memory components of the second group, and a controller for enabling one of the plurality of the NAND-type flash memory components according to the mode control signal, the zone address data and the address data, and one of the first through third latches, in order to instruct one mode among a word mode, a half-word mode for upper eight bits, a byte mode, and a standby mode for awaiting a data input and output with respect to all the NAND-type flash memory components, and for storing and outputting the information data according to the instruction data and the address data applied via the input and output bus. The NAND-type flash memory IC card can be made into a large capacity, and provides an effect of storing and outputting data which is transmitted in parallel in units of a word or a byte.

摘要翻译： NAND型闪存集成电路卡由输入和输出总线组成，输入和输出总线具有用于具有第一和第二组的多个NAND型闪存组件的第一行，用于区域地址数据的第一行，指令数据，地址数据和信息 数据和第二行，用于在第一组和第一组的NAND型闪存组件之间传送数据的第一缓冲器，用于在第一行和NAND- 类型的闪存组件，用于在第二组和第二组的NAND型闪速存储器组件之间传送数据的第三缓冲器，以及用于使多个NAND型闪存组件 根据模式控制信号，区域地址数据和地址数据以及第一到第三锁存器之一，以便在字模式，半字模式， 高八位，字节模式和待机模式，用于等待所有NAND型闪速存储器组件的数据输入和输出，并且用于根据指令数据和经过地址处理的地址数据存储和输出信息数据 输入和输出总线。 NAND型闪存IC卡可以制成大容量，并且提供存储和输出以字或字节为单位并行发送的数据的效果。