公开(公告)号：US6077573A

公开(公告)日：2000-06-20

申请号：US83350

申请日：1998-05-22

申请人： Young-sun Kim ,  Sang-hyeop Lee ,  Seung-hwan Lee ,  Young-wook Park ,  Mikio Takagi

发明人： Young-sun Kim ,  Sang-hyeop Lee ,  Seung-hwan Lee ,  Young-wook Park ,  Mikio Takagi

IPC分类号： H01L27/04 ,  C23C16/24 ,  H01L21/205 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H05H1/24

CPC分类号： C23C16/24

摘要： A method of forming a microelectronic device includes the step of forming an impurity doped amorphous silicon layer on a microelectronic substrate using plasma-enhanced chemical vapor deposition. The impurity doped amorphous silicon layer is patterned so that portions of the microelectronic substrate are exposed adjacent the patterned amorphous silicon layer. A hemispherical grained silicon layer is then formed on the patterned amorphous silicon layer. Moreover, the step of forming the impurity doped amorphous silicon layer can be performed at a temperature of 400.degree. C. or less.

摘要翻译： 形成微电子器件的方法包括使用等离子体增强化学气相沉积在微电子衬底上形成掺杂杂质的非晶硅层的步骤。 图案化杂质掺杂非晶硅层，使得微电子衬底的部分暴露在图案化的非晶硅层附近。 然后在图案化的非晶硅层上形成半球形的硅层。 此外，形成杂质掺杂非晶硅层的步骤可以在400℃以下的温度下进行。

公开(公告)号：US06573168B2

公开(公告)日：2003-06-03

申请号：US09866323

申请日：2001-05-25

申请人： Ji-soo Kim ,  Chang-woong Chu ,  Dong-hyun Kim ,  Yong-chul Oh ,  Hyoung-joon Kim ,  Byeong-yun Nam ,  Kyung-won Park ,  Sang-hyeop Lee

发明人： Ji-soo Kim ,  Chang-woong Chu ,  Dong-hyun Kim ,  Yong-chul Oh ,  Hyoung-joon Kim ,  Byeong-yun Nam ,  Kyung-won Park ,  Sang-hyeop Lee

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L21/76801 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.