公开(公告)号：US09971505B2

公开(公告)日：2018-05-15

申请号：US14986773

申请日：2016-01-04

申请人： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

发明人： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04

CPC分类号： G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/00012

摘要： Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.

公开(公告)号：US20160117110A1

公开(公告)日：2016-04-28

申请号：US14986773

申请日：2016-01-04

申请人： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

发明人： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

IPC分类号： G06F3/06

CPC分类号： G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/00012

摘要： Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.

摘要翻译： 提供内存系统。 存储器系统可以包括多个非易失性存储器和被配置为控制多个非易失性存储器的存储器控​​制器。 此外，存储器系统可以包括连接在存储器控制器和多个非易失性存储器之间的输入/输出缓冲器电路。 数据通道可以连接在存储器控制器和输入/输出缓冲器电路之间，并且第一和第二内部数据通道可以连接在输入/输出缓冲器电路和多个非易失性存储器的相应的第一和第二组之间。 输入/输出缓冲器电路可以被配置为将数据信道连接到第一和第二内部数据信道之一。

公开(公告)号：US10777269B2

公开(公告)日：2020-09-15

申请号：US16299669

申请日：2019-03-12

申请人： Jiwan Jung ,  Anil Kavala ,  Taesung Lee ,  Jeongdon Ihm

发明人： Jiwan Jung ,  Anil Kavala ,  Taesung Lee ,  Jeongdon Ihm

IPC分类号： G11C13/00

摘要： A semiconductor memory device may include banks. A sensor is disposed adjacent to the banks and configured to sense a temperature. An address buffer is configured to receive an address from an external device. A first demultiplexer is configured to transfer a row address in the address to one of the banks. A second demultiplexer is configured to transfer a column address in the address to one of the banks. A command buffer is configured to receive a command from the external device. A control logic block is configured to control the first and second demultiplexers and the banks in accordance with the command and bank information in the address. A data buffer is configured to exchange data signals between the banks and the external device. The control logic block may be further configured to transfer information on the temperature to the external device.