公开(公告)号：US07755396B2

公开(公告)日：2010-07-13

申请号：US11741995

申请日：2007-04-30

申请人： Youngsoo Shin ,  Hyung-Ock Kim

发明人： Youngsoo Shin ,  Hyung-Ock Kim

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： G11C5/063 ,  Y10T307/383 ,  Y10T307/642

摘要： A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell generates the virtual supply voltage from a second supply voltage and provides the standard cell with the virtual supply voltage in response to a control signal. The virtual supply voltage and the first supply voltage are provided by a first metal layer and the second supply voltage is provided by a third metal layer. The power gating cell may include at least one slice block and isolator blocks. The respective slice block has a transistor for switching current. The isolator blocks are arranged on both sides of the slice block and insulate the slice block from outside.

摘要翻译： 公开了一种使用电源门控的低功率半导体存储器件。 半导体存储器件包括标准单元和电源门控单元。 标准单元具有虚拟电源电压和第一电源电压。 电源门控单元从第二电源电压产生虚拟电源电压，并响应于控制信号向标准单元提供虚拟电源电压。 虚拟电源电压和第一电源电压由第一金属层提供，第二电源电压由第三金属层提供。 功率门控单元可以包括至少一个切片块和隔离块。 各个切片块具有用于切换电流的晶体管。 隔离块被布置在切片块的两侧，并将切片块与外部绝缘。

公开(公告)号：US07948263B2

公开(公告)日：2011-05-24

申请号：US12719472

申请日：2010-03-08

申请人： Hyung-Ock Kim ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Mun-Jun Seo ,  Youngsoo Shin

发明人： Hyung-Ock Kim ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Mun-Jun Seo ,  Youngsoo Shin

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0016 ,  H03K19/0013

摘要： A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.

摘要翻译： 电源门控电路包括逻辑电路，开关元件和保持触发器。 逻辑电路耦合在第一电源轨和虚拟电源轨之间。 响应于指示活动模式或待机模式的模式控制信号，开关元件将虚拟电源轨选择性地耦合到第二电源轨。 保持触发器响应于虚拟电源轨的电压选择性地执行触发器操作或数据保持操作。

公开(公告)号：US20100231255A1

公开(公告)日：2010-09-16

申请号：US12719472

申请日：2010-03-08

申请人： Hyung-Ock Kim ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Jun Seomun ,  Youngsoo Shin

发明人： Hyung-Ock Kim ,  Jung-Yun Choi ,  Bong-Hyun Lee ,  Jun Seomun ,  Youngsoo Shin

IPC分类号： H03K19/003

CPC分类号： H03K19/0016 ,  H03K19/0013

摘要： A power gating circuit includes a logic circuit, a switching element and a retention flip-flop. The logic circuit is coupled between a first power rail and a virtual power rail. The switching element selectively couples the virtual power rail to a second power rail in response to a mode control signal indicating an active mode or a standby mode. The retention flip-flop selectively performs a flip-flop operation or a data retention operation in response to a voltage of the virtual power rail.

摘要翻译： 电源门控电路包括逻辑电路，开关元件和保持触发器。 逻辑电路耦合在第一电源轨和虚拟电源轨之间。 响应于指示活动模式或待机模式的模式控制信号，开关元件将虚拟电源轨选择性地耦合到第二电源轨。 保持触发器响应于虚拟电源轨的电压选择性地执行触发器操作或数据保持操作。

公开(公告)号：US20080012424A1

公开(公告)日：2008-01-17

申请号：US11741995

申请日：2007-04-30

申请人： Youngsoo Shin ,  Hyung-Ock Kim

发明人： Youngsoo Shin ,  Hyung-Ock Kim

IPC分类号： H02J1/04

CPC分类号： G11C5/063 ,  Y10T307/383 ,  Y10T307/642

摘要： A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell generates the virtual supply voltage from a second supply voltage and provides the standard cell with the virtual supply voltage in response to a control signal. The virtual supply voltage and the first supply voltage are provided by a first metal layer and the second supply voltage is provided by a third metal layer. The power gating cell may include at least one slice block and isolator blocks. The respective slice block has a transistor for switching current. The isolator blocks are arranged on both sides of the slice block and insulate the slice block from outside.

摘要翻译： 公开了一种使用电源门控的低功率半导体存储器件。 半导体存储器件包括标准单元和电源门控单元。 标准单元具有虚拟电源电压和第一电源电压。 电源门控单元从第二电源电压产生虚拟电源电压，并响应于控制信号向标准单元提供虚拟电源电压。 虚拟电源电压和第一电源电压由第一金属层提供，第二电源电压由第三金属层提供。 功率门控单元可以包括至少一个切片块和隔离块。 各个切片块具有用于切换电流的晶体管。 隔离块被布置在切片块的两侧，并将切片块与外部绝缘。

公开(公告)号：US07296251B2

公开(公告)日：2007-11-13

申请号：US10853370

申请日：2004-05-25

申请人： Nagashyamala R. Dhanwada ,  Youngsoo Shin ,  Jingcao Hu

发明人： Nagashyamala R. Dhanwada ,  Youngsoo Shin ,  Jingcao Hu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Voltage islands enable a core-level power optimization of ASIC/SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage island partitions and the voltage level assignment are performed simultaneously in a floorplanning context due to the physical constraints involved. This leads to a floorplanning formulation that differs from the conventional floorplanning for ASIC designs. Such a formulation of a physically aware voltage island partitioning and method for performing simultaneous voltage island partitioning, level assignment and floorplanning are described, as are the definition and the solution of floorplanning for voltage island based designs executed under area, power, timing and physical constraints. The physical planning of voltage islands includes: a) characterizing cell clusters in terms of voltages and power consumption values; b) providing a set of cell clusters that belong to a single voltage island Random Logic Macro (RLM); and c) assigning voltages for the voltage island RLMs, all within the context of generating a physically realizable floorplan for the design.

摘要翻译： 电压岛可以通过为设计的每个集群使用独特的电源电压，实现ASIC / SoC设计的核心级功耗优化。 在芯片设计中创建电压岛以优化总功耗包括产生电压岛分区，分配电压电平和布局规划。 由于所涉及的物理限制，在布局规划环境中同时执行电压岛分区的产生和电压电平分配。 这导致了与ASIC设计的常规布局规划不同的布局规划。 描述了用于执行同时电压岛划分，电平分配和布局规划的物理感知电压岛划分和方法的这种制定，以及在区域，功率，定时和物理约束下执行的基于电压岛的设计的布局规划的定义和解决方案 。 电压岛的物理规划包括：a）在电压和功耗值方面表征电池组; b）提供属于单电压岛随机逻辑宏（RLM）的一组单元簇; 以及c）为电压岛RLM分配电压，所有这些电压都在为设计产生物理上可实现的平面图的上下文中。

公开(公告)号：US07616048B2

公开(公告)日：2009-11-10

申请号：US11849486

申请日：2007-09-04

申请人： Byunghee Choi ,  Jun Seomun ,  Jung-yun Choi ,  Hyo-sig Won ,  Youngsoo Shin

发明人： Byunghee Choi ,  Jun Seomun ,  Jung-yun Choi ,  Hyo-sig Won ,  Youngsoo Shin

IPC分类号： H03K3/01

CPC分类号： H03K19/00384 ,  G05F3/205 ,  H03K2217/0018

摘要： A body biasing control circuit capable of being shared by a plurality of macro blocks and can independently control body voltages of a plurality of macro blocks. The body biasing control circuit includes a lookup table for storing a plurality of indexes where each index is associated with a body voltage appropriate for an operating state of a corresponding macro block. A control unit receives a corresponding index from the lookup table and generates a plurality of body voltages appropriate for an operating state of a macro block corresponding to the index and supplies the body voltages to the macro block.

摘要翻译： 一种能够被多个宏块共享的主体偏置控制电路，并且可以独立地控制多个宏块的体电压。 身体偏置控制电路包括用于存储多个索引的查找表，其中每个索引与适于相应的宏块的操作状态的体电压相关联。 控制单元从查找表接收相应的索引，并产生适合于与索引相对应的宏块的操作状态的多个体电压，并将体电压提供给宏块。

公开(公告)号：US20050278676A1

公开(公告)日：2005-12-15

申请号：US10853370

申请日：2004-05-25

申请人： Nagashyamala Dhanwada ,  Youngsoo Shin ,  Jingcao Hu

发明人： Nagashyamala Dhanwada ,  Youngsoo Shin ,  Jingcao Hu

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5068

摘要： Voltage islands enable a core-level power optimization of ASIC/SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage island partitions and the voltage level assignment are performed simultaneously in a floorplanning context due to the physical constraints involved. This leads to a floorplanning formulation that differs from the conventional floorplanning for ASIC designs. Such a formulation of a physically aware voltage island partitioning and method for performing simultaneous voltage island partitioning, level assignment and floorplanning are described, as are the definition and the solution of floorplanning for voltage island based designs executed under area, power, timing and physical constraints. The physical planning of voltage islands includes: a) characterizing cell clusters in terms of voltages and power consumption values; b) providing a set of cell clusters that belong to a single voltage island Random Logic Macro (RLM); and c) assigning voltages for the voltage island RLMs, all within the context of generating a physically realizable floorplan for the design.

摘要翻译： 电压岛可以通过为设计的每个集群使用独特的电源电压，实现ASIC / SoC设计的核心级功耗优化。 在芯片设计中创建电压岛以优化总功耗包括产生电压岛分区，分配电压电平和布局规划。 由于所涉及的物理限制，在布局规划环境中同时执行电压岛分区的产生和电压电平分配。 这导致了与ASIC设计的常规布局规划不同的布局规划。 描述了用于执行同时电压岛划分，电平分配和布局规划的物理感知电压岛划分和方法的这种制定，以及在区域，功率，定时和物理约束下执行的基于电压岛的设计的布局规划的定义和解决方案 。 电压岛的物理规划包括：a）在电压和功耗值方面表征电池组; b）提供属于单电压岛随机逻辑宏（RLM）的一组单元簇; 以及c）为电压岛RLM分配电压，所有这些电压都在为设计产生物理上可实现的平面图的上下文中。