公开(公告)号：US20120039141A1

公开(公告)日：2012-02-16

申请号：US13209010

申请日：2011-08-12

申请人： Yu Hwan RO ,  Beak Hyung CHO ,  Ki Whan SONG ,  Young Don CHOI

发明人： Yu Hwan RO ,  Beak Hyung CHO ,  Ki Whan SONG ,  Young Don CHOI

IPC分类号： G11C7/12

CPC分类号： G11C11/4094 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4097

摘要： A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.

摘要翻译： 提供了一种存储器件，其包括多个全局位线，放电线，配置成响应于放电使能信号将多个全局位线连接到放电线的开关电路，配置为施加的第一放电电路 第一电压，其高于对所述放电线的接地电压;预充电电路，被配置为对所述多个全局位线中的所选择的全局位线施加预充电电压;以及第二放电电路，被配置为将所选择的全局位 线路到高于接地电压的第二电压。