公开(公告)号：US20060038711A1

公开(公告)日：2006-02-23

申请号：US11196273

申请日：2005-08-04

Applicant: Yu Pin Chou ,  An Shih Lee ,  Tsu Chun Wang ,  Jui Yuan Tsai

Inventor： Yu Pin Chou ,  An Shih Lee ,  Tsu Chun Wang ,  Jui Yuan Tsai

IPC: H03M1/12

CPC classification number: H03M1/0624 ,  H03M1/12

Abstract: An apparatus for channel balancing of a multi-channel analog-to-digital converter of a digital image display comprises a red, a green and a blue analog-to-digital converter for respectively receiving a red, a green and a blue analog signal of an image signal wherein the analog-to-digital converters respectively sample the red, green and blue analog signals through a sampling clock signal and output a corresponding digital signal. A phase difference processing unit is used for estimating the phase differences among the digital signals and outputting corresponding time delay signals according to the phase differences. A clock delay compensation unit is used for receiving the time delay signals and respectively compensating the time delays of the sampling clock signals of the analog-to-digital converters according to the time delay signals, thereby decreasing the phase differences among the digital signals. The present invention also provides a method for channel balancing of a multi-channel analog-to-digital converter of a digital image display.

Abstract translation: 用于数字图像显示器的多通道模数转换器的通道平衡的装置包括红色，绿色和蓝色模数转换器，用于分别接收红色，绿色和蓝色模拟信号 图像信号，其中模数转换器分别通过采样时钟信号对红色，绿色和蓝色模拟信号进行采样，并输出相应的数字信号。 相位差处理单元用于估计数字信号之间的相位差并根据相位差输出相应的时间延迟信号。 时钟延迟补偿单元用于接收时间延迟信号并根据时间延迟信号分别补偿模数转换器的采样时钟信号的时间延迟，从而减小数字信号之间的相位差。 本发明还提供了一种用于数字图像显示器的多通道模数转换器的通道平衡的方法。

公开(公告)号：US07893997B2

公开(公告)日：2011-02-22

申请号：US11273885

申请日：2005-11-15

Applicant: Yu Pin Chou

Inventor： Yu Pin Chou

IPC: H04N7/01 ,  H04N11/20 ,  H04N5/08 ,  H04N9/74 ,  H04N3/14 ,  H03L7/00 ,  G09G5/02

CPC classification number: G09G5/008 ,  H03L7/0991 ,  H03L7/18

Abstract: A method for generating a video clock and an associated target image frame is disclosed. The method generates an output clock signal for outputting a target image frame to a panel according to a frame pixel number and a vertical synchronization signal (Vsync). The target image frame corresponds to a source image frame. The frame pixel number is the number of total pixels included in a predetermined frame format, and the Vsync signal is an input Vsync signal or an output Vsync signal. The period of the output clock signal is the result of the period of the Vsync divided by the frame pixel number. In this manner, the format of the target image frame can remain substantially fixed, and is substantially equal to the predetermined frame format.

Abstract translation: 公开了一种用于产生视频时钟和相关联的目标图像帧的方法。 该方法根据帧像素数和垂直同步信号（Vsync）产生用于将目标图像帧输出到面板的输出时钟信号。 目标图像帧对应于源图像帧。 帧像素数是包括在预定帧格式中的总像素数，Vsync信号是输入Vsync信号或输出Vsync信号。 输出时钟信号的周期是Vsync的周期除以帧像素数的结果。 以这种方式，目标图像帧的格式可以保持基本上固定，并且基本上等于预定的帧格式。

公开(公告)号：US07489316B2

公开(公告)日：2009-02-10

申请号：US11222899

申请日：2005-09-08

Applicant: Jin Sheng Gong ,  Yu Pin Chou ,  Shiu Rong Tong

Inventor： Jin Sheng Gong ,  Yu Pin Chou ,  Shiu Rong Tong

IPC: G09G5/399 ,  G06F13/372

CPC classification number: H04N7/0105 ,  H04N7/0127

Abstract: A method for converting a frame rate of a video signal comprising a data enable signal by means of a first buffer and a second buffer is disclosed. The method comprises: alternatively accessing the first buffer and the second buffer according to a first frame rate; determining an accessing time point of the first and the second buffers according to the data enable signal; and accessing the buffer, which is one of the first and the second buffers and not accessed at the accessing time point, according to a second frame rate, wherein the second frame rate is faster than the first frame rate.

Abstract translation: 公开了一种通过第一缓冲器和第二缓冲器来转换包括数据使能信号的视频信号的帧速率的方法。 该方法包括：根据第一帧速率交替地访问第一缓冲器和第二缓冲器; 根据数据使能信号确定第一和第二缓冲器的访问时间点; 以及根据第二帧速率访问作为第一和第二缓冲器之一并且在访问时间点未被访问的缓冲器，其中第二帧速率比第一帧速率快。

公开(公告)号：US07483768B2

公开(公告)日：2009-01-27

申请号：US11166203

申请日：2005-06-27

Applicant: Yu Pin Chou

Inventor： Yu Pin Chou

IPC: G06F19/00

CPC classification number: G11C5/14

Abstract: An adaptive power managing device for an IC chip or a circuit system comprises a tunable voltage generator, a data generator, a data processing unit, a data checking unit and a control unit; the tunable voltage generator is used for providing the IC chip or the circuit system with an operating voltage; the data generator is used for generating a series of predetermined data to the data processing unit; the data processing unit is used for processing the series of predetermined data and then outputting a series of output data associated with the series of predetermined data; and the data checking unit is used for checking the validity of the series of output data; wherein if the series of output data is checked to be invalid, the control unit outputs a control signal for tuning up the operating voltage; if the series of output data is checked to be valid, the operating voltage is maintained or the control unit outputs another control signal for tuning down the operating voltage whereby efficiently achieving the objective of power management. The present invention also provides an adaptive power managing method.

Abstract translation: 一种用于IC芯片或电路系统的自适应功率管理装置，包括可调电压发生器，数据发生器，数据处理单元，数据检查单元和控制单元; 可调电压发生器用于为IC芯片或电路系统提供工作电压; 数据发生器用于向数据处理单元生成一系列预定数据; 数据处理单元用于处理一系列预定数据，然后输出与一系列预定数据相关联的一系列输出数据; 数据检查单元用于检查一系列输出数据的有效性; 其中如果所述一系列输出数据被检查为无效，则所述控制单元输出用于调谐所述工作电压的控制信号; 如果一系列输出数据被检查为有效，则维持工作电压，或者控制单元输出另一控制信号以调低工作电压，从而有效地实现电源管理的目的。 本发明还提供一种自适应功率管理方法。