Power-on reset circuit
    1.
    发明授权
    Power-on reset circuit 有权
    上电复位电路

    公开(公告)号:US08446189B2

    公开(公告)日:2013-05-21

    申请号:US12794227

    申请日:2010-06-04

    IPC分类号: H03L7/00

    CPC分类号: H03K17/20

    摘要: A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

    摘要翻译: 上电复位电路包括钳位信号发生器和确定装置。 钳位信号发生器适于接收触发信号,并且参考触发信号产生钳位信号。 钳位信号发生器包括用于根据反馈信号产生钳位信号的输出单元和用于根据第一和第二中间信号产生反馈信号的反馈单元。 参考钳位信号产生第一中间信号。 根据触发信号产生第二中间信号。 确定装置适于接收触发信号,耦合到钳位信号发生器用于从其接收钳位信号,并且可操作以根据触发信号和钳位信号产生复位信号。

    POWER-ON RESET CIRCUIT
    2.
    发明申请
    POWER-ON RESET CIRCUIT 有权
    上电复位电路

    公开(公告)号:US20100308877A1

    公开(公告)日:2010-12-09

    申请号:US12794227

    申请日:2010-06-04

    IPC分类号: H03L7/00

    CPC分类号: H03K17/20

    摘要: A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

    摘要翻译: 上电复位电路包括钳位信号发生器和确定装置。 钳位信号发生器适于接收触发信号,并且参考触发信号产生钳位信号。 钳位信号发生器包括用于根据反馈信号产生钳位信号的输出单元和用于根据第一和第二中间信号产生反馈信号的反馈单元。 参考钳位信号产生第一中间信号。 根据触发信号产生第二中间信号。 确定装置适于接收触发信号,耦合到钳位信号发生器用于从其接收钳位信号,并且可操作以根据触发信号和钳位信号产生复位信号。

    Image encoding/decoding device and method thereof with data blocks in a determined order
    3.
    发明授权
    Image encoding/decoding device and method thereof with data blocks in a determined order 有权
    图像编码/解码装置及其方法,其具有确定顺序的数据块

    公开(公告)号:US08036476B2

    公开(公告)日:2011-10-11

    申请号:US11874214

    申请日:2007-10-18

    IPC分类号: G06K9/36

    摘要: The invention provides an image encoding/decoding device and method. An encoding/decoding architecture of the invention includes: encoders for encoding image data into data blocks; a reordering multiplexer for receiving the data blocks and determining an order by which the data blocks are written into a memory according to an order of an achieved percentage of an encoding progress for each encoder; a memory writing unit, a memory dispatcher, a memory controller, and a memory reading unit, for writing the data blocks into the memory and reading the data blocks from the memory; a request demultiplexer for receiving the read data blocks from the memory reading unit and outputting the received data blocks according to data request signals; and decoders for generating the data request signals, receiving the output data blocks from the request demultiplexer, decoding the received data blocks, and then outputting the decoded data blocks.

    摘要翻译: 本发明提供一种图像编码/解码装置和方法。 本发明的编码/解码架构包括:用于将图像数据编码成数据块的编码器; 重新排序多路复用器,用于接收数据块,并根据每个编码器的编码进程的实现百分比的顺序确定将数据块写入存储器的顺序; 存储器写入单元,存储器调度器,存储器控制器和存储器读取单元,用于将数据块写入存储器并从存储器读取数据块; 请求解复用器,用于从存储器读取单元接收读取的数据块,并根据数据请求信号输出接收到的数据块; 以及用于产生数据请求信号的解码器,从请求解复用器接收输出数据块,对接收到的数据块进行解码,然后输出解码的数据块。

    Display controller having an embedded non-volatile memory divided into a program code block and a data block and method for updating parameters of the same
    4.
    发明授权
    Display controller having an embedded non-volatile memory divided into a program code block and a data block and method for updating parameters of the same 有权
    具有划分为程序代码块的嵌入式非易失性存储器和用于更新其参数的数据块和方法的显示控制器

    公开(公告)号:US08914602B2

    公开(公告)日:2014-12-16

    申请号:US11594068

    申请日:2006-11-08

    摘要: A controller and a method of updating parameters on the same. The controller includes an embedded non-volatile memory, a programming circuit, an embedded SRAM, a MCU (Micro Computer Unit), and a memory controller. The embedded non-volatile memory has a program code block for storing program codes to be executed by the MCU, and a data block for storing the parameters. The MCU writes the parameters into the data block of the flash memory through the memory controller, or reads data in the data block of the non-volatile memory through the memory controller. Because the controller does not need to employ an external EEPROM, the cost can be reduced and the speed for accessing the parameters can be increased.

    摘要翻译: 控制器和更新参数的方法。 控制器包括嵌入式非易失性存储器,编程电路,嵌入式SRAM,MCU(微计算机单元)和存储器控制器。 嵌入式非易失性存储器具有用于存储要由MCU执行的程序代码的程序代码块和用于存储参数的数据块。 MCU通过存储器控制器将参数写入闪存的数据块,或通过存储器控制器读取非易失性存储器的数据块中的数据。 由于控制器不需要使用外部EEPROM,因此可以降低成本,并且可以提高访问参数的速度。

    IMAGE ENCODING/DECODING DEVICE AND METHOD THEREOF
    5.
    发明申请
    IMAGE ENCODING/DECODING DEVICE AND METHOD THEREOF 有权
    图像编码/解码装置及其方法

    公开(公告)号:US20080095454A1

    公开(公告)日:2008-04-24

    申请号:US11874214

    申请日:2007-10-18

    IPC分类号: G06K9/00

    摘要: The invention provides an image encoding/decoding device and method. An encoding/decoding architecture of the invention includes: encoders for encoding image data into data blocks; a reordering multiplexer for receiving the data blocks and determining an order by which the data blocks are written into a memory according to an order of an achieved percentage of an encoding progress for each encoder; a memory writing unit, a memory dispatcher, a memory controller, and a memory reading unit, for writing the data blocks into the memory and reading the data blocks from the memory; a request demultiplexer for receiving the read data blocks from the memory reading unit and outputting the received data blocks according to data request signals; and decoders for generating the data request signals, receiving the output data blocks from the request demultiplexer, decoding the received data blocks, and then outputting the decoded data blocks.

    摘要翻译: 本发明提供一种图像编码/解码装置和方法。 本发明的编码/解码架构包括:用于将图像数据编码成数据块的编码器; 重新排序多路复用器,用于接收数据块,并根据每个编码器的编码进程的实现百分比的顺序确定将数据块写入存储器的顺序; 存储器写入单元,存储器调度器,存储器控制器和存储器读取单元,用于将数据块写入存储器并从存储器读取数据块; 请求解复用器,用于从存储器读取单元接收读取的数据块,并根据数据请求信号输出接收到的数据块; 以及用于产生数据请求信号的解码器,从请求解复用器接收输出数据块,对接收到的数据块进行解码,然后输出解码的数据块。

    Display controller and method of updating parameters of the same
    6.
    发明申请
    Display controller and method of updating parameters of the same 有权
    显示控制器和更新参数的方法

    公开(公告)号:US20070106835A1

    公开(公告)日:2007-05-10

    申请号:US11594068

    申请日:2006-11-08

    IPC分类号: G06F12/00

    摘要: A controller and a method of updating parameters on the same. The controller includes an embedded non-volatile memory, a programming circuit, an embedded SRAM, a MCU (Micro Computer Unit), and a memory controller. The embedded non-volatile memory has a program code block for storing program codes to be executed by the MCU, and a data block for storing the parameters. The MCU writes the parameters into the data block of the flash memory through the memory controller, or reads data in the data block of the non-volatile memory through the memory controller. Because the controller does not need to employ an external EEPROM, the cost can be reduced and the speed for accessing the parameters can be increased.

    摘要翻译: 控制器和更新参数的方法。 控制器包括嵌入式非易失性存储器,编程电路,嵌入式SRAM,MCU(微计算机单元)和存储器控制器。 嵌入式非易失性存储器具有用于存储要由MCU执行的程序代码的程序代码块和用于存储参数的数据块。 MCU通过存储器控制器将参数写入闪存的数据块,或通过存储器控制器读取非易失性存储器的数据块中的数据。 由于控制器不需要使用外部EEPROM,因此可以降低成本,并且可以提高访问参数的速度。

    Device and method for 3-D display control
    7.
    发明授权
    Device and method for 3-D display control 有权
    3-D显示控制的设备和方法

    公开(公告)号:US08482603B2

    公开(公告)日:2013-07-09

    申请号:US13179810

    申请日:2011-07-11

    CPC分类号: H04N13/341

    摘要: A representative Device and Method for 3-D Display Control is disclosed. The method for controlling stereo image display is disclosed. That is, to receive an image input signal wherein the image input signal includes a first refresh rate; to convert a frame rate of the image input signal to generate an image output signal, wherein the image output signal includes a second refresh rate which is higher than the first refresh rate, and includes a first image signal, a first VBI (Vertical Blanking Interval), a second image signal, a second VBI, a third image signal and a third VBI; to output a control signal for a left eye shutter of shutter glasses during a duration between the first VBI and a part of the second image signal; and to output a control signal for a right eye shutter of the shutter glasses during a duration between a part of the third image signal and the third VBI.

    摘要翻译: 公开了一种用于3D显示控制的代表性装置和方法。 公开了用于控制立体图像显示的方法。 也就是说,接收图像输入信号,其中图像输入信号包括第一刷新率; 转换图像输入信号的帧速率以产生图像输出信号,其中图像输出信号包括高于第一刷新率的第二刷新率,并且包括第一图像信号,第一VBI(垂直消隐间隔 ),第二图像信号,第二VBI,第三图像信号和第三VBI; 在第一VBI和第二图像信号的一部分之间的持续时间期间输出用于快门眼镜的左眼快门的控制信号; 并且在第三图像信号的一部分和第三VBI之间的持续时间期间输出用于快门眼镜的右眼快门的控制信号。

    Eyeglasses
    8.
    外观设计

    公开(公告)号:USD544517S1

    公开(公告)日:2007-06-12

    申请号:US29226894

    申请日:2005-04-04

    申请人: Wen-Che Wu

    设计人: Wen-Che Wu

    DEVICE AND METHOD FOR 3-D DISPLAY CONTROL
    9.
    发明申请
    DEVICE AND METHOD FOR 3-D DISPLAY CONTROL 有权
    3-D显示控制的装置和方法

    公开(公告)号:US20130016195A1

    公开(公告)日:2013-01-17

    申请号:US13560590

    申请日:2012-07-27

    IPC分类号: H04N13/04

    CPC分类号: H04N13/341

    摘要: A control device for three dimensional display has an image processor and a timing signal generator. The image processor is used for receiving a first and a second input image signals to generate a first, a second, and a third output image signals. The first output image signal comprises part of the first input image signal. The second output image signal comprises part of the first input image signal and part of the second input image signal. The third output image signal comprises part of the second input image signal. The timing signal generator is used for generating a first lens control signal for configuring a first lens to be non-opaque when the second output image signal is displayed on a display device, and generating a second lens control signal for configuring a second lens to be non-opaque when the third output image signal is displayed on the display device.

    摘要翻译: 用于三维显示的控制装置具有图像处理器和定时信号发生器。 图像处理器用于接收第一和第二输入图像信号以产生第一,第二和第三输出图像信号。 第一输出图像信号包括第一输入图像信号的一部分。 第二输出图像信号包括第一输入图像信号的一部分和第二输入图像信号的一部分。 第三输出图像信号包括第二输入图像信号的一部分。 定时信号发生器用于产生第一透镜控制信号,用于在第二输出图像信号显示在显示装置上时将第一透镜配置为不透明,并且产生用于将第二透镜配置为第二透镜控制信号 当第三输出图像信号显示在显示装置上时,不透明。

    Eyeglasses
    10.
    外观设计

    公开(公告)号:USD553174S1

    公开(公告)日:2007-10-16

    申请号:US29226895

    申请日:2005-04-04

    申请人: Wen-Che Wu

    设计人: Wen-Che Wu