公开(公告)号：US20120056652A1

公开(公告)日：2012-03-08

申请号：US13024287

申请日：2011-02-09

申请人： Yu-Sheng Lai ,  Feng-Chia Chang ,  Chun Shiah

发明人： Yu-Sheng Lai ,  Feng-Chia Chang ,  Chun Shiah

IPC分类号： H03L7/08 ,  H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/10

摘要： A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.

摘要翻译： 动态调整相位追踪速度以提高DLL电路的效率的方法包括检测DLL电路中的输入时钟信号的总体环路延迟，根据总体环路延迟获得最佳因数，并且在锁相周期 根据最佳因数除去输入时钟信号的频率和对应于输入时钟信号的反馈时钟信号。

公开(公告)号：US08384454B2

公开(公告)日：2013-02-26

申请号：US13024287

申请日：2011-02-09

申请人： Yu-Sheng Lai ,  Feng-Chia Chang ,  Chun Shiah

发明人： Yu-Sheng Lai ,  Feng-Chia Chang ,  Chun Shiah

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/10

摘要： A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.

摘要翻译： 动态调整相位追踪速度以提高DLL电路的效率的方法包括检测DLL电路中的输入时钟信号的总体环路延迟，根据总体环路延迟获得最佳因数，并且在锁相周期 根据最佳因数除去输入时钟信号的频率和对应于输入时钟信号的反馈时钟信号。

公开(公告)号：US20120229106A1

公开(公告)日：2012-09-13

申请号：US13099375

申请日：2011-05-03

申请人： Yu-Sheng Lai ,  Feng-Chia Chang ,  Yu-Chou Ke

发明人： Yu-Sheng Lai ,  Feng-Chia Chang ,  Yu-Chou Ke

IPC分类号： G05F1/10

CPC分类号： G05F1/563

摘要： A regulator includes a first amplifier, a second amplifier, a current control circuit, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, and a feedback circuit. The current control circuit includes a controller and at least one switch, and a second terminal of the first P-type metal-oxide-semiconductor transistor is coupled to a second terminal of the second P-type metal-oxide-semiconductor transistor. The regulator utilizes the controller to turn off the at least one switch during operation of the regulator in a light load mode, and the regulator utilizes the controller to turn on the at least one switch in turn when the regulator changes from the light load mode to a heavy load mode. Thus, the regulator can quickly recover a load current in the heavy load mode.

摘要翻译： 调节器包括第一放大器，第二放大器，电流控制电路，第一P型金属氧化物半导体晶体管，第二P型金属氧化物半导体晶体管和反馈电路。 电流控制电路包括控制器和至少一个开关，第一P型金属氧化物半导体晶体管的第二端子耦合到第二P型金属氧化物半导体晶体管的第二端子。 调节器利用控制器在轻负载模式下操作调节器期间关闭至少一个开关，并且当调节器从轻负载模式改变为轻负载模式时，调节器利用控制器依次打开至少一个开关 重负载模式。 因此，调节器可以在重负载模式下快速恢复负载电流。

公开(公告)号：US20120169379A1

公开(公告)日：2012-07-05

申请号：US13050969

申请日：2011-03-18

申请人： Yu-Sheng Lai ,  Feng-Chia Chang

发明人： Yu-Sheng Lai ,  Feng-Chia Chang

IPC分类号： G11C27/02

CPC分类号： H03L7/10 ,  H03L7/0812 ,  H03L2207/08

摘要： A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.

摘要翻译： 电压保持电路包括四个开关，运算放大器和电容器。 通过打开和关闭开关，运算放大器用作单位增益缓冲器。 在正常工作模式下，运算放大器的正输入端耦合到一个节点，运算放大器的输出端耦合到电容器。 因此，电容器的电压等于节点的电压。 在断电模式下，运算放大器的正输入端耦合到电容器，运算放大器的输出端耦合到节点。 因此，节点的电压等于电容器的电压。 因此，电压保持电路能够将节点的电压保持在掉电状态。

公开(公告)号：US08330513B2

公开(公告)日：2012-12-11

申请号：US13050969

申请日：2011-03-18

申请人： Yu-Sheng Lai ,  Feng-Chia Chang

发明人： Yu-Sheng Lai ,  Feng-Chia Chang

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/0812 ,  H03L2207/08

摘要： A voltage hold circuit includes four switches, an operational amplifier and a capacitor. By turning the switches on and off, the operational amplifier functions as a unity-gain buffer. In the normal operation mode, the positive input end of the operational amplifier is coupled to a node, and the output end of the operational amplifier is coupled to the capacitor. Thus the voltage of the capacitor is equal to the voltage of the node. In the power off mode, the positive input end of the operational amplifier is coupled d to the capacitor, and the output end of the operational amplifier is coupled to the node. Thus the voltage of the node is equal to the voltage of the capacitor. Therefore, the voltage hold circuit is able to hold the voltage of the node in the power down state.

摘要翻译： 电压保持电路包括四个开关，运算放大器和电容器。 通过打开和关闭开关，运算放大器用作单位增益缓冲器。 在正常工作模式下，运算放大器的正输入端耦合到一个节点，运算放大器的输出端耦合到电容器。 因此，电容器的电压等于节点的电压。 在断电模式下，运算放大器的正输入端耦合到电容器，运算放大器的输出端耦合到节点。 因此，节点的电压等于电容器的电压。 因此，电压保持电路能够将节点的电压保持在掉电状态。

公开(公告)号：US08773089B2

公开(公告)日：2014-07-08

申请号：US13099375

申请日：2011-05-03

申请人： Yu-Sheng Lai ,  Feng-Chia Chang ,  Yu-Chou Ke

发明人： Yu-Sheng Lai ,  Feng-Chia Chang ,  Yu-Chou Ke

IPC分类号： G05F1/00 ,  G05F1/563

CPC分类号： G05F1/563

摘要： A regulator includes a first amplifier, a second amplifier, a current control circuit, a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, and a feedback circuit. The current control circuit includes a controller and at least one switch, and a second terminal of the first P-type metal-oxide-semiconductor transistor is coupled to a second terminal of the second P-type metal-oxide-semiconductor transistor. The regulator utilizes the controller to turn off the at least one switch during operation of the regulator in a light load mode, and the regulator utilizes the controller to turn on the at least one switch in turn when the regulator changes from the light load mode to a heavy load mode. Thus, the regulator can quickly recover a load current in the heavy load mode.

摘要翻译： 调节器包括第一放大器，第二放大器，电流控制电路，第一P型金属氧化物半导体晶体管，第二P型金属氧化物半导体晶体管和反馈电路。 电流控制电路包括控制器和至少一个开关，第一P型金属氧化物半导体晶体管的第二端子耦合到第二P型金属氧化物半导体晶体管的第二端子。 调节器利用控制器在轻负载模式下操作调节器期间关闭至少一个开关，并且当调节器从轻负载模式改变为轻负载模式时，调节器利用控制器依次打开至少一个开关 重负载模式。 因此，调节器可以在重负载模式下快速恢复负载电流。

公开(公告)号：US08432206B2

公开(公告)日：2013-04-30

申请号：US13425379

申请日：2012-03-20

申请人： Der-Min Yuan ,  Kuang-Fu Teng ,  Chun Shiah ,  Feng-Chia Chang

发明人： Der-Min Yuan ,  Kuang-Fu Teng ,  Chun Shiah ,  Feng-Chia Chang

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L1/02

摘要： A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.

摘要翻译： 延迟锁定环路系统包括时序控制器，或门，输入缓冲器，脉冲发生器和延迟锁定环。 定时控制器用于在省电信号处于逻辑低电压的同时周期性地输出外部使能信号，并且根据省电信号的逻辑高电压被禁用。 脉冲发生器用于根据省电信号的上升沿产生脉冲。 OR门耦合到定时控制器，用于接收功率节省信号，脉冲和外部使能信号，并根据功率节省信号和外部使能信号输出使能信号。 延迟锁定环路被耦合到或门和输入缓冲器，以根据使能信号再次启用延迟锁定环路。

公开(公告)号：US20120256666A1

公开(公告)日：2012-10-11

申请号：US13425379

申请日：2012-03-20

申请人： Der-Min Yuan ,  Kuang-Fu Teng ,  Chun Shiah ,  Feng-Chia Chang

发明人： Der-Min Yuan ,  Kuang-Fu Teng ,  Chun Shiah ,  Feng-Chia Chang

IPC分类号： H03L7/08

CPC分类号： H03L7/0812 ,  H03L1/02

摘要： A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.

摘要翻译： 延迟锁定环路系统包括时序控制器，或门，输入缓冲器，脉冲发生器和延迟锁定环。 定时控制器用于在省电信号处于逻辑低电压的同时周期性地输出外部使能信号，并且根据省电信号的逻辑高电压被禁用。 脉冲发生器用于根据省电信号的上升沿产生脉冲。 OR门耦合到定时控制器，用于接收功率节省信号，脉冲和外部使能信号，并根据功率节省信号和外部使能信号输出使能信号。 延迟锁定环路被耦合到或门和输入缓冲器，以根据使能信号再次启用延迟锁定环路。

公开(公告)号：US20100019819A1

公开(公告)日：2010-01-28

申请号：US12252347

申请日：2008-10-15

申请人： Chun-Peng Wu ,  Chun Shiah ,  Feng-Chia Chang

发明人： Chun-Peng Wu ,  Chun Shiah ,  Feng-Chia Chang

IPC分类号： H03H11/26

CPC分类号： H03K5/13 ,  H03K2005/00078 ,  H03K2005/00156

摘要： Constant delay circuit includes signal input end, delay signal output end, RC delay circuit, and a comparator. The signal input end receives an input signal. The delay signal output end outputs the delay input signal, which the delay period is predetermined. The RC delay circuit is coupled to the signal input end for receiving the input signal and generating a voltage. The comparator includes a first input end, a second input end, and an output end. The first end of the comparator is coupled to the RC delay circuit for receiving the voltage. The second end of the comparator receives a reference voltage. The output end of the comparator is coupled to the delay signal output end of the long delay circuit. The comparator compares the reference voltage and the voltage, and accordingly generates a result as the delay signal.

摘要翻译： 恒定延迟电路包括信号输入端，延迟信号输出端，RC延迟电路和比较器。 信号输入端接收输入信号。 延迟信号输出端输出预定延迟时间的延迟输入信号。 RC延迟电路耦合到信号输入端，用于接收输入信号并产生电压。 比较器包括第一输入端，第二输入端和输出端。 比较器的第一端耦合到用于接收电压的RC延迟电路。 比较器的第二端接收参考电压。 比较器的输出端耦合到长延迟电路的延迟信号输出端。 比较器比较参考电压和电压，并因此产生作为延迟信号的结果。

公开(公告)号：US07750683B2

公开(公告)日：2010-07-06

申请号：US12252329

申请日：2008-10-15

申请人： Hsien-Sheng Huang ,  Feng-Chia Chang

发明人： Hsien-Sheng Huang ,  Feng-Chia Chang

IPC分类号： H03D13/00

CPC分类号： H03D13/00 ,  H03L7/089

摘要： PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.

摘要翻译： PFD包括UP和DOWN信号模块以及RESET信号模块。 UP和DOWN信号模块根据参考和反馈时钟信号发送UP和DOWN信号。 RESET模块包括UP-RESET和DOWN-RESET信号模块。 UP-RESET信号模块根据预触发反馈信号，UP和DOWN信号复位UP信号模块。 根据原始反馈时钟信号和逻辑门和反相延迟模块的计算产生预触发反馈信号。 DOWN-RESET信号模块根据预触发参考信号，UP和DOWN信号复位DOWN信号模块。 根据原始参考时钟信号和逻辑门和反相延迟模块的计算产生预触发参考信号。