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    Lead-frame-based semiconductor package and lead frame thereof
    2.
    发明申请
    Lead-frame-based semiconductor package and lead frame thereof 审中-公开
    基于引线框架的半导体封装及其引线框架

    公开(公告)号：US20060151862A1

    公开(公告)日：2006-07-13

    申请号：US11071389

    申请日：2005-03-02

    申请人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

    发明人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49503 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A lead-frame-based semiconductor package and a lead frame thereof are proposed. The semiconductor package includes: the lead frame having at least one die pad and a plurality of leads around the die pad, wherein a plurality of grooves and runners are formed on a surface of the die pad, and each of the grooves is connected to an edge of the die pad by at least one of the runners; at least one chip mounted on the other surface of the die pad and electrically connected to the plurality of leads; and an encapsulant for encapsulating the chip, with the runners and grooves being exposed from the encapsulant. Thus, the flash problem in the prior art can be solved by means of the runners and grooves.

    摘要翻译： 提出了一种引线框架半导体封装及其引线框架。 所述半导体封装包括：所述引线框架具有至少一个管芯焊盘和围绕所述管芯焊盘的多个引线，其中在所述管芯焊盘的表面上形成多个沟槽和流道，并且每个所述沟槽连接到 由至少一个跑步者的模具垫的边缘; 至少一个芯片安装在所述管芯焊盘的另一个表面上并电连接到所述多个引线; 以及用于封装芯片的密封剂，其中流道和凹槽从密封剂暴露出来。 因此，现有技术中的闪光灯问题可以通过滑道和槽来解决。

    Synchronous DRAM with alternated data line sensing
    4.
    发明授权
    Synchronous DRAM with alternated data line sensing 失效
    具有交替数据线感测的同步DRAM

    公开(公告)号：US5812473A

    公开(公告)日：1998-09-22

    申请号：US746655

    申请日：1996-11-13

    申请人： Terry Tsai

    发明人： Terry Tsai

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1006 ,  G11C7/1072

    摘要： A synchronous dynamic random access memory (SDRAM) has a plurality of memory cell arrays including a plurality of bit line pairs with each bit line connected to a plurality of memory cells, a plurality of sense amplifiers with each sense amplifier connected to a bit line pair of each memory cell array through a bank select switch, and a plurality of data line pairs. A plurality of pass gates includes a first pair of pass gates connecting a sense amplifier output of a bit line pair to a first data line pair, and a second pair of pass gates connecting the sense amplifier output of a bit line pair to a second data line pair, whereby each bit line pair is connectable through a sense amplifier to first and second data line pairs. In operation, the first data line pair and the second data line pair are toggled alternately in connection to the bit line pairs by alternating column select line signals (CSLA, CSLB).

    摘要翻译： 同步动态随机存取存储器（SDRAM）具有多个存储单元阵列，其包括多个位线对，每个位线连接到多个存储单元;多个读出放大器，每个读出放大器连接到位线对 每个存储单元阵列通过存储体选择开关，以及多个数据线对。 多个通过门包括将位线对的读出放大器输出连接到第一数据线对的第一对通孔和将位线对的读出放大器输出连接到第二数据的第二对通孔 线对，由此每个位线对可通过读出放大器连接到第一和第二数据线对。 在操作中，通过交替列选择线信号（CSLA，CSLB），第一数据线对和第二数据线对被交替地与位线对交替地切换。