公开(公告)号：US08975734B2

公开(公告)日：2015-03-10

申请号：US12967839

申请日：2010-12-14

申请人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/02 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/81395 ,  H01L2224/81439 ,  H01L2224/83395 ,  H01L2224/83439 ,  H01L2224/85001 ,  H01L2224/85395 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.

摘要翻译： 其上形成有芯片载体的半导体封装及其制造方法。 金属载体被半蚀刻以形成对应于凹槽的多个凹槽和金属螺柱。 凹槽填充有第一密封剂，并且在金属螺柱上形成多个接合焊盘。 第一密封剂直接与金属螺栓结合。 每个接合焊盘和对应于接合焊盘的一个金属螺柱形成T形结构。 因此，金属螺柱和第一密封剂之间的结合力增强，从而避免分层。 随后进行模具安装，引线接合和成型工艺。 由于半蚀刻槽被第一密封剂填充，因此克服了使现有技术中遇到的导致难以进行运输的柔韧金属载体的缺陷，并且通过不需要使用昂贵的金属来促进制造成本 抗蚀剂层。

公开(公告)号：US08624368B2

公开(公告)日：2014-01-07

申请号：US12843440

申请日：2010-07-26

申请人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

发明人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

IPC分类号： H01L23/28

CPC分类号： H01L21/561 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/552 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.

摘要翻译： 四通道扁平无引线（QFN）半导体封装包括管芯焊盘; 设置在管芯焊盘周边的I / O连接; 安装在芯片焊盘上的芯片; 接合线; 用于封装芯片焊盘的密封剂，I / O连接，芯片和接合线，同时暴露管芯焊盘的底表面和I / O连接; 形成在管芯焊盘的底部表面上的表面层和I / O连接; 形成在密封剂和表面层的底表面上并具有用于暴露表面层的开口的电介质层。 表面层与电介质层具有良好的结合，有助于防止回流工艺中的焊料渗透到芯片焊盘中并防止焊料挤出在I / O连接和电介质层的界面上，从而提高产品产量。

公开(公告)号：US20110221059A1

公开(公告)日：2011-09-15

申请号：US12825513

申请日：2010-06-29

申请人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

发明人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

IPC分类号： H01L23/49 ,  H01L21/60

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A QFN package includes a chip-mounting base; electrically connecting pads disposed around the periphery of the chip-mounting base, the bottom surfaces of the chip-mounting base and the electrically connecting pads being covered by a copper layer; a chip mounted on the top surface of the chip-mounting base; bonding wires electrically connecting to the chip and the electrically connecting pads; an encapsulant encapsulating the chip-mounting base, the electrically connecting pads, the chip and the bonding wires while exposing the copper layer; and a dielectric layer formed on the bottom surfaces of the encapsulant and the copper layer and having a plurality of openings exposing a portion of the copper layer. The copper layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the interface between the chip-mounting base, the electrically connecting pads and the dielectric layer, thereby avoiding solder extrusion and enhancing product yield.

摘要翻译： QFN封装包括芯片安装基座; 设置在芯片安装基座的周边周围的电连接焊盘，芯片安装基座的底面和电连接焊盘被铜层覆盖; 安装在芯片安装基座的顶表面上的芯片; 电连接到芯片和电连接焊盘的接合线; 在暴露铜层的同时封装芯片安装基座，电连接焊盘，芯片和接合线的密封剂; 以及形成在密封剂和铜层的底表面上并且具有暴露铜层的一部分的多个开口的电介质层。 铜层与电介质层具有良好的结合，有助于防止回流工艺中的焊料渗透到芯片安装基座，电连接焊盘和电介质层之间的界面，从而避免焊料挤出并提高产品产量。

公开(公告)号：US20110221049A1

公开(公告)日：2011-09-15

申请号：US12843440

申请日：2010-07-26

申请人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

发明人： Fu-Di Tang ,  Ching-Chiuan Wei ,  Yung-Chih Lin

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49582 ,  H01L23/552 ,  H01L24/89 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.

摘要翻译： 四通道扁平无引线（QFN）半导体封装包括管芯焊盘; 设置在管芯焊盘周边的I / O连接; 安装在芯片焊盘上的芯片; 接合线; 用于封装芯片焊盘的密封剂，I / O连接，芯片和接合线，同时暴露管芯焊盘的底表面和I / O连接; 形成在管芯焊盘的底部表面上的表面层和I / O连接; 形成在密封剂和表面层的底表面上并具有用于暴露表面层的开口的电介质层。 表面层与电介质层具有良好的结合，有助于防止回流工艺中的焊料渗透到芯片焊盘中并防止焊料挤出在I / O连接和电介质层的界面上，从而提高产品产量。

公开(公告)号：US07893547B2

公开(公告)日：2011-02-22

申请号：US11164322

申请日：2005-11-18

申请人： Chien-Ping Huang ,  Fu-Di Tang

发明人： Chien-Ping Huang ,  Fu-Di Tang

IPC分类号： H01L23/28

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions.

摘要翻译： 提供了具有支撑结构的半导体封装及其制造方法。 通过将芯片电连接到形成在载体上的电触头，进行成型工艺。 形成在载体上的多个凹部填充有用于在模制过程中封装芯片的密封剂。 在移除载体之后，填充凹部的密封剂的一部分在密封剂的表面上形成向外突出的部分，使得半导体封装可以经由突出部分附接到外部装置。

公开(公告)号：US07679172B2

公开(公告)日：2010-03-16

申请号：US11488689

申请日：2006-07-19

申请人： Chien-Ping Huang ,  Fu-Di Tang ,  Yuan-Chun Li

发明人： Chien-Ping Huang ,  Fu-Di Tang ,  Yuan-Chun Li

IPC分类号： H01L23/495

CPC分类号： H01L21/6835 ,  H01L21/4821 ,  H01L21/568 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2221/68345 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/83851 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package without a chip carrier includes an insulating structure having an opening; an electroplated die pad provided in the opening; a chip attached to the electroplated die pad by a thermally conductive adhesive; a plurality of electrical contacts formed around the electroplated die pad, wherein at least one of the electrical contacts is provided on a top surface of the insulating structure, and the chip is electrically connected to the electrical contacts; and an encapsulant for encapsulating the chip, the insulating structure and the electrical contacts, wherein bottom surfaces of the insulating structure, the electroplated die pad and the electrical contacts, except the at least one electrical contact provided on the top surface of the insulating structure, are exposed from the encapsulant and are flush with a bottom surface of the encapsulant. A fabrication method of the semiconductor package is also provided.

摘要翻译： 没有芯片载体的半导体封装包括具有开口的绝缘结构; 设置在开口中的电镀模片垫; 通过导热粘合剂附着到电镀模片垫的芯片; 形成在所述电镀管芯焊盘周围的多个电触点，其中所述电触头中的至少一个设置在所述绝缘结构的顶表面上，并且所述芯片电连接到所述电触头; 以及用于封装所述芯片，所述绝缘结构和所述电触点的密封剂，其中所述绝缘结构的底表面，所述电镀芯片焊盘和所述电触点除了设置在所述绝缘结构的顶表面上的所述至少一个电触点之外， 从密封剂暴露并与密封剂的底表面齐平。 还提供了半导体封装的制造方法。

公开(公告)号：US07314820B2

公开(公告)日：2008-01-01

申请号：US11042939

申请日：2005-01-24

申请人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

发明人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

IPC分类号： H01L21/44 ,  H01L21/50 ,  H01L21/48 ,  H01L23/52 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/85001 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.

摘要翻译： 提供了一种无载体半导体封装及其制造方法。 该制造方法包括以下步骤：提供其上形成有多个电触头的载体; 在载体上安装至少一个芯片; 通过多个接合线将芯片电连接到电触点; 在每个所述电触点上形成涂层，以将每个所述接合线的接合端封装在所述电触点上; 进行成型工艺以形成用于封装芯片，接合线和电触头的密封剂; 并移除载体，使得电触点的底表面从密封剂暴露出来。 这获得不具有载体的半导体封装，并且涂层可以增强电触点和密封剂之间的粘附。

公开(公告)号：US20070007669A1

公开(公告)日：2007-01-11

申请号：US11521792

申请日：2006-09-15

申请人： Chin-Teng Hsu ,  Ming-Chun Laio ,  Holman Chen ,  Chun-Yuan Li ,  Fu-Di Tang

发明人： Chin-Teng Hsu ,  Ming-Chun Laio ,  Holman Chen ,  Chun-Yuan Li ,  Fu-Di Tang

IPC分类号： H01L23/52

CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A wire-bonding method and a semiconductor package using the same are provided. The semiconductor package includes a carrier; a chip mounted on the carrier; a plurality of first wires and second wires alternatively arranged in a stagger manner, with a wire loop of each second wire being downwardly bent to form a deformed portion so as to provide a height different between the wire loops of each first wire and each second wire, wherein the first and second wires electrically connect the chip to the carrier; and an encapsulant for encapsulating the chip, the first wires, the second wires and a portion of the carrier. The height difference between the wire loops of each first wire and each second wire increases a pitch between adjacent first and second wires thereby preventing the wires from contact and short circuit with each other due to wire sweep during an encapsulation process.

摘要翻译： 提供引线接合方法和使用其的半导体封装。 半导体封装包括载体; 安装在载体上的芯片; 以交错的方式交替布置的多个第一线和第二线，每条第二线的线环向下弯曲以形成变形部分，以便提供在每个第一线和每条第二线的线环之间不同的高度 ，其中所述第一和第二线将所述芯片电连接到所述载体; 以及用于封装芯片，第一布线，第二布线和托架的一部分的密封剂。 每个第一线和每个第二线的线环之间的高度差增加相邻的第一和第二线之间的间距，从而防止线在封装过程中由于电线扫描而彼此接触和短路。

公开(公告)号：US20050173791A1

公开(公告)日：2005-08-11

申请号：US10894925

申请日：2004-07-19

申请人： Chin-Teng Hsu ,  Ming-Chun Laio ,  Holman Chen ,  Chun-Yuan Li ,  Fu-Di Tang

发明人： Chin-Teng Hsu ,  Ming-Chun Laio ,  Holman Chen ,  Chun-Yuan Li ,  Fu-Di Tang

IPC分类号： H01L21/56 ,  H01L23/48 ,  H01L23/495

CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A wire-bonding method and a semiconductor package using the same are provided. The semiconductor package includes a carrier; a chip mounted on the carrier; a plurality of first wires and second wires alternatively arranged in a stagger manner, with a wire loop of each second wire being downwardly bent to form a deformed portion so as to provide a height different between the wire loops of each first wire and each second wire, wherein the first and second wires electrically connect the chip to the carrier; and an encapsulant for encapsulating the chip, the first wires, the second wires and a portion of the carrier. The height difference between the wire loops of each first wire and each second wire increases a pitch between adjacent first and second wires thereby preventing the wires from contact and short circuit with each other due to wire sweep during an encapsulation process.

摘要翻译： 提供引线接合方法和使用其的半导体封装。 半导体封装包括载体; 安装在载体上的芯片; 以交错的方式交替布置的多个第一线和第二线，每条第二线的线环向下弯曲以形成变形部分，以便提供在每个第一线和每条第二线的线环之间不同的高度 ，其中所述第一和第二线将所述芯片电连接到所述载体; 以及用于封装芯片，第一布线，第二布线和托架的一部分的密封剂。 每个第一线和每个第二线的线环之间的高度差增加相邻的第一和第二线之间的间距，从而防止线在封装过程中由于电线扫描而彼此接触和短路。

公开(公告)号：US08390118B2

公开(公告)日：2013-03-05

申请号：US12859635

申请日：2010-08-19

申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

摘要翻译： 具有电连接结构的半导体封装包括：具有管芯焊盘和围绕管芯焊盘的迹线的导电层; 一个芯片 接合线; 具有多个空腔的密封剂，其深度大于管芯焊盘的厚度，以及用于将管芯焊盘和其中的迹线嵌入其中的迹线，以及使裸片焊盘和迹线露出的空腔; 形成在所述空腔中的焊料掩模层，并且具有用于暴露所述迹线端部和所述管芯焊盘的一部分的多个开口; 以及形成在开口中并电连接到迹线端的焊球。 将焊料掩模层与密封剂接合，增强了焊料掩模层的粘合强度，从而延长了水分渗透路径并提高了封装的可靠性。