公开(公告)号：US07934313B1

公开(公告)日：2011-05-03

申请号：US12759237

申请日：2010-04-13

申请人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H05K3/30

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A fabrication method of a package structure includes: preparing a metal plate having first and second surfaces and defined with an active region; forming a wiring layer with conductive traces and first electrical contact pads on the first surface; forming third electrical contact pads corresponding to the first electrical contact pads on the second surface; forming a first encapsulant on the first surface; forming on the second surface an open area to penetrate the metal plate, wherein the metal plate form conductive posts between the first and third electrical contact pads; mounting in the open area a chip electrically connected to the wiring layer; forming a second encapsulant in the open area, the wiring layer and the third electrical contact pads; forming first and second openings in the first and second encapsulants to expose the third electrical contact pads, respectively; and cutting the metal plate to remove the metal layer.

摘要翻译： 包装结构的制造方法包括：制备具有第一表面和第二表面并且限定有活性区域的金属板; 在所述第一表面上形成具有导电迹线和第一电接触焊盘的布线层; 形成对应于第二表面上的第一电接触焊盘的第三电接触焊盘; 在所述第一表面上形成第一密封剂; 在所述第二表面上形成穿透所述金属板的开放区域，其中所述金属板在所述第一和第三电接触焊盘之间形成导电柱; 在所述开放区域中安装与所述布线层电连接的芯片; 在所述开放区域中形成第二密封剂，所述布线层和所述第三电接触焊盘; 在第一和第二密封剂中形成第一和第二开口以分别露出第三电接触垫; 并切割金属板以去除金属层。

公开(公告)号：US20090039488A1

公开(公告)日：2009-02-12

申请号：US12228379

申请日：2008-08-11

申请人： Chang-Yueh Chan ,  Chih-Ming Huang ,  Chun-Yuan Li ,  Chih-Hsin Lai

发明人： Chang-Yueh Chan ,  Chih-Ming Huang ,  Chun-Yuan Li ,  Chih-Hsin Lai

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/89 ,  H01L21/561 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.

摘要翻译： 提供半导体封装及其制造方法。 提供了包括管芯焊盘和多个外围引线的引线框架。 具有形成在其上的多个连接焊盘的载体被附接到管芯焊盘，其中载体的平面尺寸大于管芯焊盘的平面尺寸，允许载体上的连接焊盘从裸片焊盘露出。 至少一个半导体芯片附着到包括芯片焊盘和载体的组件的一侧，并通过接合线电连接到载体和引线的连接焊盘。 封装密​​封剂封装半导体芯片，接合线，载体的一部分和引线框架的一部分，允许载体的底表面和引线的一部分从封装密封剂暴露。

公开(公告)号：US20110156227A1

公开(公告)日：2011-06-30

申请号：US12770028

申请日：2010-04-29

申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/495

CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

摘要翻译： 半导体封装结构包括：电介质层; 设置在电介质层上并具有芯片焊盘和迹线的金属层，每个迹线包括迹线体，延伸到管芯焊盘周边的接合焊盘和相对的迹线端; 金属柱贯穿电介质层，其一端连接到管芯焊盘并且其端部从电介质层突出; 半导体芯片，安装在芯片焊盘上，并通过接合线电连接到焊盘; 以及覆盖半导体芯片，接合线，金属层和电介质层的密封剂。 本发明的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免在现有技术中遇到的焊料桥接。

公开(公告)号：US20080303134A1

公开(公告)日：2008-12-11

申请号：US12156875

申请日：2008-06-05

申请人： Chun-Yuan Li ,  Hsiao-Jen Hung ,  Chin-Huang Chang ,  Jeng-Yuan Lai

发明人： Chun-Yuan Li ,  Hsiao-Jen Hung ,  Chin-Huang Chang ,  Jeng-Yuan Lai

IPC分类号： H01L23/52 ,  H01L21/02

CPC分类号： H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/27 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H05K3/341 ,  H05K3/3436 ,  H05K2201/0373 ,  H05K2201/09472 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a method for fabricating the same are disclosed, which includes: providing a carrier board, forming a plurality of metal bumps on the carrier board, forming a metal layer on the carrier board to encapsulate the metal bumps, having at least one semiconductor chip electrically connected to the metal layer, then forming an encapsulant on the carrier board to encapsulate the semiconductor chip, and next removing the carrier board and the metal bumps to correspondingly form a plurality of grooves on surface of the encapsulant, wherein bottom and sides of the grooves are covered with the metal layer to allow electroconductive components to be effectively positioned in the grooves and completely bonded with the metal layer.

摘要翻译： 公开了一种半导体封装及其制造方法，其包括：提供载体板，在载体板上形成多个金属凸块，在载体板上形成金属层以封装金属凸块，具有至少一个 半导体芯片与金属层电连接，然后在载体板上形成密封剂以封装半导体芯片，接着去除载体板和金属凸块，以在密封剂的表面上相应地形成多个凹槽，其中底部和侧面 的沟槽被金属层覆盖以允许导电部件有效地定位在槽中并与金属层完全粘合。

公开(公告)号：US08873244B2

公开(公告)日：2014-10-28

申请号：US12759117

申请日：2010-04-13

申请人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Hsiao-Jen Hung ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.

摘要翻译： 封装结构包括具有第一密封剂和嵌入第一密封剂并暴露于第一密封剂的布线层的基体。 布线层具有多个导电迹线和多个第一电接触焊盘。 第一密封剂具有用于暴露第一电接触焊盘的开口，与布线层电连接的芯片，以及形成在基体上的用于覆盖芯片和布线层的第二密封剂，从而提供均匀的表面，以防止密封剂 芯片安装时开裂。

公开(公告)号：US08618641B2

公开(公告)日：2013-12-31

申请号：US12228379

申请日：2008-08-11

申请人： Chang-Yueh Chan ,  Chih-Ming Huang ,  Chun-Yuan Li ,  Chih-Hsin Lai

发明人： Chang-Yueh Chan ,  Chih-Ming Huang ,  Chun-Yuan Li ,  Chih-Hsin Lai

IPC分类号： H01L23/495

CPC分类号： H01L24/89 ,  H01L21/561 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.

摘要翻译： 提供半导体封装及其制造方法。 提供了包括管芯焊盘和多个外围引线的引线框架。 具有形成在其上的多个连接焊盘的载体被附接到管芯焊盘，其中载体的平面尺寸大于管芯焊盘的平面尺寸，允许载体上的连接焊盘从裸片焊盘露出。 至少一个半导体芯片附着到包括芯片焊盘和载体的组件的一侧，并通过接合线电连接到载体和引线的连接焊盘。 封装密​​封剂封装半导体芯片，接合线，载体的一部分和引线框架的一部分，允许载体的底表面和引线的一部分从封装密封剂暴露。

公开(公告)号：US08304268B2

公开(公告)日：2012-11-06

申请号：US12770059

申请日：2010-04-29

申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L21/44

CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.

摘要翻译： 半导体封装结构的制造方法包括：图案化具有第一表面和第二表面的金属板; 在所述金属板上形成电介质层; 在所述第一表面和所述电介质层上形成金属层; 在所述第二表面上形成金属焊盘，所述金属层具有管芯焊盘并且各自具有接合焊盘; 将半导体芯片安装在芯片焊盘上，然后通过接合线将半导体芯片电连接到焊盘; 形成密封剂以覆盖半导体芯片和金属层; 去除未被金属垫覆盖的金属板的部分，以形成金属柱; 并执行单独处理。 该制造方法的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免焊料桥接。

公开(公告)号：US07314820B2

公开(公告)日：2008-01-01

申请号：US11042939

申请日：2005-01-24

申请人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

发明人： Yu-Wei Lin ,  Fu-Di Tang ,  Chun-Yuan Li ,  Terry Tsai ,  Yu-Ting Ho

IPC分类号： H01L21/44 ,  H01L21/50 ,  H01L21/48 ,  H01L23/52 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/85001 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A carrier-free semiconductor package and a fabrication method thereof are provided. The fabrication method includes the steps of: providing a carrier having a plurality of electrical contacts formed thereon; mounting at least one chip on the carrier; electrically connecting the chip to the electrical contacts via a plurality of bonding wires; forming a coating layer on each of the electrical contacts to encapsulate a bonded end of each of the bonding wires on the electrical contacts; performing a molding process to form an encapsulant for encapsulating the chip, the bonding wires and the electrical contacts; and removing the carrier, such that bottom surfaces of the electrical contacts are exposed from the encapsulant. This obtains a semiconductor package not having a carrier, and the coating layers can enhance adhesion between the electrical contacts and the encapsulant.

摘要翻译： 提供了一种无载体半导体封装及其制造方法。 该制造方法包括以下步骤：提供其上形成有多个电触头的载体; 在载体上安装至少一个芯片; 通过多个接合线将芯片电连接到电触点; 在每个所述电触点上形成涂层，以将每个所述接合线的接合端封装在所述电触点上; 进行成型工艺以形成用于封装芯片，接合线和电触头的密封剂; 并移除载体，使得电触点的底表面从密封剂暴露出来。 这获得不具有载体的半导体封装，并且涂层可以增强电触点和密封剂之间的粘附。

公开(公告)号：US20070007669A1

公开(公告)日：2007-01-11

申请号：US11521792

申请日：2006-09-15

申请人： Chin-Teng Hsu ,  Ming-Chun Laio ,  Holman Chen ,  Chun-Yuan Li ,  Fu-Di Tang

发明人： Chin-Teng Hsu ,  Ming-Chun Laio ,  Holman Chen ,  Chun-Yuan Li ,  Fu-Di Tang

IPC分类号： H01L23/52

CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A wire-bonding method and a semiconductor package using the same are provided. The semiconductor package includes a carrier; a chip mounted on the carrier; a plurality of first wires and second wires alternatively arranged in a stagger manner, with a wire loop of each second wire being downwardly bent to form a deformed portion so as to provide a height different between the wire loops of each first wire and each second wire, wherein the first and second wires electrically connect the chip to the carrier; and an encapsulant for encapsulating the chip, the first wires, the second wires and a portion of the carrier. The height difference between the wire loops of each first wire and each second wire increases a pitch between adjacent first and second wires thereby preventing the wires from contact and short circuit with each other due to wire sweep during an encapsulation process.

摘要翻译： 提供引线接合方法和使用其的半导体封装。 半导体封装包括载体; 安装在载体上的芯片; 以交错的方式交替布置的多个第一线和第二线，每条第二线的线环向下弯曲以形成变形部分，以便提供在每个第一线和每条第二线的线环之间不同的高度 ，其中所述第一和第二线将所述芯片电连接到所述载体; 以及用于封装芯片，第一布线，第二布线和托架的一部分的密封剂。 每个第一线和每个第二线的线环之间的高度差增加相邻的第一和第二线之间的间距，从而防止线在封装过程中由于电线扫描而彼此接触和短路。

公开(公告)号：US20050173791A1

公开(公告)日：2005-08-11

申请号：US10894925

申请日：2004-07-19

申请人： Chin-Teng Hsu ,  Ming-Chun Laio ,  Holman Chen ,  Chun-Yuan Li ,  Fu-Di Tang

发明人： Chin-Teng Hsu ,  Ming-Chun Laio ,  Holman Chen ,  Chun-Yuan Li ,  Fu-Di Tang

IPC分类号： H01L21/56 ,  H01L23/48 ,  H01L23/495

CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L23/4952 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A wire-bonding method and a semiconductor package using the same are provided. The semiconductor package includes a carrier; a chip mounted on the carrier; a plurality of first wires and second wires alternatively arranged in a stagger manner, with a wire loop of each second wire being downwardly bent to form a deformed portion so as to provide a height different between the wire loops of each first wire and each second wire, wherein the first and second wires electrically connect the chip to the carrier; and an encapsulant for encapsulating the chip, the first wires, the second wires and a portion of the carrier. The height difference between the wire loops of each first wire and each second wire increases a pitch between adjacent first and second wires thereby preventing the wires from contact and short circuit with each other due to wire sweep during an encapsulation process.

摘要翻译： 提供引线接合方法和使用其的半导体封装。 半导体封装包括载体; 安装在载体上的芯片; 以交错的方式交替布置的多个第一线和第二线，每条第二线的线环向下弯曲以形成变形部分，以便提供在每个第一线和每条第二线的线环之间不同的高度 ，其中所述第一和第二线将所述芯片电连接到所述载体; 以及用于封装芯片，第一布线，第二布线和托架的一部分的密封剂。 每个第一线和每个第二线的线环之间的高度差增加相邻的第一和第二线之间的间距，从而防止线在封装过程中由于电线扫描而彼此接触和短路。