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    Method and apparatus for multi-mode driver
    1.
    发明授权
    Method and apparatus for multi-mode driver 有权
    多模式驱动程序的方法和装置

    公开(公告)号：US07183805B2

    公开(公告)日：2007-02-27

    申请号：US11385234

    申请日：2006-03-20

    申请人： Yueyong Wang ,  Barry W. Daly ,  Nhat M. Nguyen ,  Yohan U. Frans

    发明人： Yueyong Wang ,  Barry W. Daly ,  Nhat M. Nguyen ,  Yohan U. Frans

    IPC分类号： H03K19/094

    CPC分类号： H04L25/0274 ,  H03K19/018585 ,  H04L25/0282 ,  H04L25/10

    摘要： Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.

    摘要翻译： 描述具有可以使用模式选择输入并且可以包括共模（CM）电压补偿机制的单个输出电路的多模式信号驱动器。 在第一示例性实施例中，多模式输出驱动器适于根据至少两种模式来驱动来自单个输出电路的信号，例如电流模式逻辑（CML）信令模式和低电压差分信号（LVDS）模式 。 在第二示例性实现中，电路包括准LVDS输出驱动器，其中差分放大器电路与可调电阻元件和可编程电流源串联连接。 在第三示例性实施方案中，输出驱动器电路的CM电压随着可编程偏置电流的改变而改变。 为了补偿，反馈机构向输出驱动器电路的可变电阻元件提供补偿信号，以维持期望的CM电压。

    Method and apparatus for multi-mode driver
    2.
    发明授权
    Method and apparatus for multi-mode driver 失效

    公开(公告)号：US07061273B2

    公开(公告)日：2006-06-13

    申请号：US10456303

    申请日：2003-06-06

    申请人： Yueyong Wang ,  Barry W. Daly ,  Nhat M. Nguyen ,  Yohan U. Frans

    发明人： Yueyong Wang ,  Barry W. Daly ,  Nhat M. Nguyen ,  Yohan U. Frans

    IPC分类号： H03K19/094

    CPC分类号： H04L25/0274 ,  H03K19/018585 ,  H04L25/0282 ,  H04L25/10

    摘要： Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.

    Method and apparatus for signal reception using ground termination and/or non-ground termination
    3.
    发明授权
    Method and apparatus for signal reception using ground termination and/or non-ground termination 有权
    使用接地端接和/或非接地端接信号接收的方法和装置

    公开(公告)号：US07102390B2

    公开(公告)日：2006-09-05

    申请号：US11058088

    申请日：2005-02-15

    申请人： Yohan U. Frans ,  Nhat M. Nguyen ,  Yueyong Wang

    发明人： Yohan U. Frans ,  Nhat M. Nguyen ,  Yueyong Wang

    IPC分类号： H03K19/0175

    CPC分类号： H04L25/0292 ,  H03K5/003 ,  H04L25/0272

    摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.

    摘要翻译： 具有可能被接地端接的输入和具有选择性地接地或非接地端接的输入的接收单元使能信号电平移位和终端模式选择输入。 在第一示例性实施方式中，接收单元能够具有接地端接的输入。 然而，输入到解码数据恢复电路的信号的共模电压高于地，因为输入信号可能在接地端接输入和解码数据恢复电路之间的电平移位。 在第二示例性实施方案中，通过将分压器切换到操作中并且绕过非接地端接模式的电平移位器来实现模式选择。 对于接地端接模式，分压器切换到运行状态，电平转换器切换到其信号输出进行操作，进行解码。 也可以使用预扩增来提高信号强度。

    Method and apparatus for signal reception using ground termination and/or non-ground termination
    4.
    发明授权
    Method and apparatus for signal reception using ground termination and/or non-ground termination 有权
    使用接地端接和/或非接地端接信号接收的方法和装置

    公开(公告)号：US06856169B2

    公开(公告)日：2005-02-15

    申请号：US10435292

    申请日：2003-05-09

    申请人： Yohan U. Frans ,  Nhat M. Nguyen ,  Yueyong Wang

    发明人： Yohan U. Frans ,  Nhat M. Nguyen ,  Yueyong Wang

    IPC分类号： H03K5/00 ,  H03K5/003 ,  H03K5/01 ,  H03K19/003 ,  H03K19/0175 ,  H04L25/02

    CPC分类号： H04L25/0292 ,  H03K5/003 ,  H04L25/0272

    摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.

    摘要翻译： 具有可能被接地端接的输入和具有选择性地接地或非接地端接的输入的接收单元使能信号电平移位和终端模式选择输入。 在第一示例性实施方式中，接收单元能够具有接地端接的输入。 然而，输入到解码数据恢复电路的信号的共模电压高于地，因为输入信号可能在接地端接输入和解码数据恢复电路之间的电平移位。 在第二示例性实施方案中，通过将分压器切换到操作中并且绕过非接地端接模式的电平移位器来实现模式选择。 对于接地端接模式，分压器切换到运行状态，电平转换器切换到其信号输出进行操作，进行解码。 也可以使用预扩增来提高信号强度。

    Supporting calibration for sub-rate operation in clocked memory systems
    8.
    发明授权
    Supporting calibration for sub-rate operation in clocked memory systems 有权
    支持定时存储器系统中子速率操作的校准

    公开(公告)号：US09036436B2

    公开(公告)日：2015-05-19

    申请号：US13982474

    申请日：2012-05-03

    申请人： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

    发明人： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

    IPC分类号： G11C7/22 ,  G11C29/02 ,  G06F1/10

    CPC分类号： G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    摘要： The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

    摘要翻译： 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2，1/4或1/8）相关联 频率）。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。