公开(公告)号：US07183805B2

公开(公告)日：2007-02-27

申请号：US11385234

申请日：2006-03-20

申请人： Yueyong Wang ,  Barry W. Daly ,  Nhat M. Nguyen ,  Yohan U. Frans

发明人： Yueyong Wang ,  Barry W. Daly ,  Nhat M. Nguyen ,  Yohan U. Frans

IPC分类号： H03K19/094

CPC分类号： H04L25/0274 ,  H03K19/018585 ,  H04L25/0282 ,  H04L25/10

摘要： Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.

摘要翻译： 描述具有可以使用模式选择输入并且可以包括共模（CM）电压补偿机制的单个输出电路的多模式信号驱动器。 在第一示例性实施例中，多模式输出驱动器适于根据至少两种模式来驱动来自单个输出电路的信号，例如电流模式逻辑（CML）信令模式和低电压差分信号（LVDS）模式 。 在第二示例性实现中，电路包括准LVDS输出驱动器，其中差分放大器电路与可调电阻元件和可编程电流源串联连接。 在第三示例性实施方案中，输出驱动器电路的CM电压随着可编程偏置电流的改变而改变。 为了补偿，反馈机构向输出驱动器电路的可变电阻元件提供补偿信号，以维持期望的CM电压。

公开(公告)号：US07061273B2

公开(公告)日：2006-06-13

申请号：US10456303

申请日：2003-06-06

申请人： Yueyong Wang ,  Barry W. Daly ,  Nhat M. Nguyen ,  Yohan U. Frans

发明人： Yueyong Wang ,  Barry W. Daly ,  Nhat M. Nguyen ,  Yohan U. Frans

IPC分类号： H03K19/094

CPC分类号： H04L25/0274 ,  H03K19/018585 ,  H04L25/0282 ,  H04L25/10

摘要： Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.

公开(公告)号：US07102390B2

公开(公告)日：2006-09-05

申请号：US11058088

申请日：2005-02-15

申请人： Yohan U. Frans ,  Nhat M. Nguyen ,  Yueyong Wang

发明人： Yohan U. Frans ,  Nhat M. Nguyen ,  Yueyong Wang

IPC分类号： H03K19/0175

CPC分类号： H04L25/0292 ,  H03K5/003 ,  H04L25/0272

摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.

摘要翻译： 具有可能被接地端接的输入和具有选择性地接地或非接地端接的输入的接收单元使能信号电平移位和终端模式选择输入。 在第一示例性实施方式中，接收单元能够具有接地端接的输入。 然而，输入到解码数据恢复电路的信号的共模电压高于地，因为输入信号可能在接地端接输入和解码数据恢复电路之间的电平移位。 在第二示例性实施方案中，通过将分压器切换到操作中并且绕过非接地端接模式的电平移位器来实现模式选择。 对于接地端接模式，分压器切换到运行状态，电平转换器切换到其信号输出进行操作，进行解码。 也可以使用预扩增来提高信号强度。

公开(公告)号：US06856169B2

公开(公告)日：2005-02-15

申请号：US10435292

申请日：2003-05-09

申请人： Yohan U. Frans ,  Nhat M. Nguyen ,  Yueyong Wang

发明人： Yohan U. Frans ,  Nhat M. Nguyen ,  Yueyong Wang

IPC分类号： H03K5/00 ,  H03K5/003 ,  H03K5/01 ,  H03K19/003 ,  H03K19/0175 ,  H04L25/02

CPC分类号： H04L25/0292 ,  H03K5/003 ,  H04L25/0272

摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.

摘要翻译： 具有可能被接地端接的输入和具有选择性地接地或非接地端接的输入的接收单元使能信号电平移位和终端模式选择输入。 在第一示例性实施方式中，接收单元能够具有接地端接的输入。 然而，输入到解码数据恢复电路的信号的共模电压高于地，因为输入信号可能在接地端接输入和解码数据恢复电路之间的电平移位。 在第二示例性实施方案中，通过将分压器切换到操作中并且绕过非接地端接模式的电平移位器来实现模式选择。 对于接地端接模式，分压器切换到运行状态，电平转换器切换到其信号输出进行操作，进行解码。 也可以使用预扩增来提高信号强度。

公开(公告)号：US20060158223A1

公开(公告)日：2006-07-20

申请号：US11385234

申请日：2006-03-20

申请人： Yueyong Wang ,  Barry Daly ,  Nhat Nguyen ,  Yohan Frans

发明人： Yueyong Wang ,  Barry Daly ,  Nhat Nguyen ,  Yohan Frans

IPC分类号： H03K19/0175

CPC分类号： H04L25/0274 ,  H03K19/018585 ,  H04L25/0282 ,  H04L25/10

摘要： Multi-mode signal drivers with a single output circuit that may be controlled using a mode select input and that may include a common mode (CM) voltage compensation mechanism are described. In a first exemplary implementation, a multi-mode output driver is adapted to drive signals from a single output circuit according to at least two modes, such as a current mode logic (CML) signaling mode and a low voltage differential signaling (LVDS) mode. In a second exemplary implementation, a circuit comprises a quasi-LVDS output driver in which a differential amplifier circuit is connected in series with an adjustable resistive element and a programmable current source. In a third exemplary implementation, a CM voltage of an output driver circuit changes with changes to a programmable bias current. To compensate, a feedback mechanism provides a compensation signal to a variable resistive element of the output driver circuit to maintain a desired CM voltage.

摘要翻译： 描述具有可以使用模式选择输入并且可以包括共模（CM）电压补偿机制的单个输出电路的多模式信号驱动器。 在第一示例性实施例中，多模式输出驱动器适于根据至少两种模式来驱动来自单个输出电路的信号，例如电流模式逻辑（CML）信令模式和低电压差分信号（LVDS）模式 。 在第二示例性实现中，电路包括准LVDS输出驱动器，其中差分放大器电路与可调电阻元件和可编程电流源串联连接。 在第三示例性实施方案中，输出驱动器电路的CM电压随着可编程偏置电流的改变而改变。 为了补偿，反馈机构向输出驱动器电路的可变电阻元件提供补偿信号，以维持期望的CM电压。

公开(公告)号：US07026848B2

公开(公告)日：2006-04-11

申请号：US10847353

申请日：2004-05-18

申请人： Yueyong Wang ,  Xudong Shi

发明人： Yueyong Wang ,  Xudong Shi

IPC分类号： H03K3/00

CPC分类号： H04L25/028 ,  H03K19/018528 ,  H04L25/0274

摘要： A pre-driver circuit for use in high speed signaling systems is disclosed. In one particular exemplary embodiment, the pre-driver circuit may comprise an input transistor, an active load, a passive load, and a current source. The input transistor has a gate terminal, a current sinking terminal, and a current sourcing terminal. The active load has a control input coupled to the gate terminal of the input transistor, a current sourcing terminal coupled to the current sinking terminal of the input transistor, and a current sinking terminal. The passive load has a first terminal coupled to the current sinking terminal of the active load and a second terminal coupled to the current sourcing terminal of the active load. The current source is coupled to the current sourcing terminal of the input transistor.

摘要翻译： 公开了一种用于高速信号传输系统的预驱动电路。 在一个特定的示例性实施例中，预驱动器电路可以包括输入晶体管，有源负载，被动负载和电流源。 输入晶体管具有栅极端子，电流吸收端子和电流源端子。 有源负载具有耦合到输入晶体管的栅极端子的控制输入端，耦合到输入晶体管的电流吸收端子的电流源端子和电流吸收端子。 无源负载具有耦合到有源负载的当前吸收端子的第一端子和耦合到有源负载的电流源端子的第二端子。 电流源耦合到输入晶体管的电流源端。

公开(公告)号：US06809569B2

公开(公告)日：2004-10-26

申请号：US10085782

申请日：2002-02-28

申请人： Yueyong Wang ,  Chanh Tran

发明人： Yueyong Wang ,  Chanh Tran

IPC分类号： H03K3017

CPC分类号： G05F3/262

摘要： A circuit includes a first node having a first variable voltage and a second node having a second variable voltage. A clock signal generates the first variable and second variable voltages. A first transistor is coupled to the first node and provides a first current responsive to a first control voltage being applied to the first transistor gate. A second transistor is coupled to the second node and provides a second current responsive to a second control voltage being applied to the second transistor gate. A first control circuit is coupled to the first transistor gate and the second node. The first control circuit provides the first control voltage responsive to the first variable voltage. A second control circuit is coupled to the second transistor gate and the first node. The second control circuit provides the second control voltage responsive to the second variable voltage. The first and second currents are used to provide a duty cycle correction signal.

摘要翻译： 电路包括具有第一可变电压的第一节点和具有第二可变电压的第二节点。 时钟信号产生第一可变电压和第二可变电压。 第一晶体管耦合到第一节点并提供响应于施加到第一晶体管栅极的第一控制电压的第一电流。 第二晶体管耦合到第二节点，并响应于施加到第二晶体管栅极的第二控制电压提供第二电流。 第一控制电路耦合到第一晶体管栅极和第二节点。 第一控制电路响应于第一可变电压提供第一控制电压。 第二控制电路耦合到第二晶体管栅极和第一节点。 第二控制电路响应于第二可变电压提供第二控制电压。 第一和第二电流用于提供占空比校正信号。

公开(公告)号：US20050258875A1

公开(公告)日：2005-11-24

申请号：US10847353

申请日：2004-05-18

申请人： Yueyong Wang ,  Xudong Shi

发明人： Yueyong Wang ,  Xudong Shi

IPC分类号： H03B1/00 ,  H03K19/0185 ,  H04L25/02

CPC分类号： H04L25/028 ,  H03K19/018528 ,  H04L25/0274

摘要： A pre-driver circuit for use in high speed signaling systems is disclosed. In one particular exemplary embodiment, the pre-driver circuit may comprise an input transistor, an active load, a passive load, and a current source. The input transistor has a gate terminal, a current sinking terminal, and a current sourcing terminal. The active load has a control input coupled to the gate terminal of the input transistor, a current sourcing terminal coupled to the current sinking terminal of the input transistor, and a current sinking terminal. The passive load has a first terminal coupled to the current sinking terminal of the active load and a second terminal coupled to the current sourcing terminal of the active load. The current source is coupled to the current sourcing terminal of the input transistor.

摘要翻译： 公开了一种用于高速信号传输系统的预驱动电路。 在一个特定的示例性实施例中，预驱动器电路可以包括输入晶体管，有源负载，被动负载和电流源。 输入晶体管具有栅极端子，电流吸收端子和电流源端子。 有源负载具有耦合到输入晶体管的栅极端子的控制输入端，耦合到输入晶体管的电流吸收端子的电流源端子和电流吸收端子。 无源负载具有耦合到有源负载的当前吸收端子的第一端子和耦合到有源负载的电流源端子的第二端子。 电流源耦合到输入晶体管的电流源端。

公开(公告)号：US20050189961A1

公开(公告)日：2005-09-01

申请号：US11058088

申请日：2005-02-15

申请人： Yohan Frans ,  Nhat Nguyen ,  Yueyong Wang

发明人： Yohan Frans ,  Nhat Nguyen ,  Yueyong Wang

IPC分类号： H03K5/00 ,  H03K5/003 ,  H03K5/01 ,  H03K19/003 ,  H03K19/0175 ,  H04L25/02

CPC分类号： H04L25/0292 ,  H03K5/003 ,  H04L25/0272

摘要： Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.

公开(公告)号：US06803823B2

公开(公告)日：2004-10-12

申请号：US10184148

申请日：2002-06-27

申请人： Yueyong Wang ,  Chanh Tran

发明人： Yueyong Wang ,  Chanh Tran

IPC分类号： H03F304

CPC分类号： H03F3/45739 ,  H03F3/45188 ,  H03F2203/45642 ,  H03F2203/45686

摘要： A circuit, apparatus and method for providing a balanced differential signal from incoming serial data having high or low voltage swings are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a voltage source and a current source coupled to a node. A first electrical path is coupled to the voltage source and the node. A second electrical path is coupled to the voltage source and the node. The first path includes a first transistor having a first gate and a first channel. The first transistor gate is adapted to receive a reference voltage. The second path includes a second transistor having a second gate and a second channel. The second transistor gate is adapted to receive a data voltage that is variable as a positive and negative voltage relative to the reference voltage. A variable resistor is coupled to the first electrical path and the second electrical path, and provides a predetermined resistance responsive to a control signal. A signal processing circuit is coupled to the variable resistor and the node. The signal processing circuit generates a control signal responsive to the node voltage.

摘要翻译： 在本发明的实施例中提供了一种用于在具有高电压或低电压摆幅的输入串行数据中提供平衡差分信号的电路，装置和方法。 在本发明的实施例中，电路包括耦合到节点的电压源和电流源。 第一电路连接到电压源和节点。 第二电路连接到电压源和节点。 第一路径包括具有第一栅极和第一沟道的第一晶体管。 第一晶体管栅极适于接收参考电压。 第二路径包括具有第二栅极和第二沟道的第二晶体管。 第二晶体管栅极适于接收相对于参考电压可变为正负电压的数据电压。 可变电阻器耦合到第一电路径和第二电路径，并且响应于控制信号提供预定电阻。 信号处理电路耦合到可变电阻器和节点。 信号处理电路响应于节点电压产生控制信号。