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公开(公告)号：US20100330782A1
公开(公告)日：2010-12-30
申请号：US12853840
申请日：2010-08-10
IPC分类号： H01L21/762 , H01L21/18
CPC分类号： H01L29/785 , H01L29/66803 , H01L29/78621
摘要： A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
摘要翻译： 在基板上形成具有上表面和侧面的半导体区域。 第一杂质区形成在半导体区域的上部。 第二杂质区域形成在半导体区域的侧部。 第二杂质区的电阻率基本上等于或小于第一杂质区的电阻率。
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公开(公告)号：US20080179683A1
公开(公告)日：2008-07-31
申请号：US12025504
申请日：2008-02-04
CPC分类号： H01L29/785 , H01L29/66803 , H01L29/78621
摘要： A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.
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公开(公告)号：US20120015504A1
公开(公告)日：2012-01-19
申请号：US13245497
申请日：2011-09-26
IPC分类号： H01L21/20 , H01L21/265
CPC分类号： H01L29/7854 , H01L29/66803
摘要： A semiconductor device includes: a first semiconductor region formed on a substrate and having an upper surface and a side surface; a first impurity region of a first conductivity type formed in an upper portion of the first semiconductor region; a second impurity region of a first conductivity type formed in a side portion of the first semiconductor region; and a gate insulating film formed so as to cover at least a side surface and an upper corner of a predetermined portion of the first semiconductor region. A radius of curvature r′ of an upper corner of a portion of the first semiconductor region located outside the gate insulating film is greater than a radius of curvature r of an upper corner of a portion of the first semiconductor region located under the gate insulating film and is less than or equal to 2r.
摘要翻译： 半导体器件包括：形成在基板上并具有上表面和侧表面的第一半导体区域; 形成在第一半导体区域的上部的第一导电类型的第一杂质区; 形成在第一半导体区域的侧部的第一导电类型的第二杂质区; 以及栅极绝缘膜，其形成为覆盖所述第一半导体区域的预定部分的至少一个侧表面和上拐角。 位于栅极绝缘膜外部的第一半导体区域的一部分的上角的曲率半径r'大于栅极绝缘膜下方的第一半导体区域的一部分的上角的曲率半径r 小于等于2r。
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4.发明申请METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE HAVE FIN-SHAPED SEMICONDUCTOR REGIONS 有权用于生产具有精细形状的半导体区域的半导体器件的方法公开(公告)号：US20110275201A1
公开(公告)日：2011-11-10
申请号：US13185221
申请日：2011-07-18
IPC分类号： H01L21/223
CPC分类号： H01L29/66803 , H01L29/66795 , H01L29/7854
摘要： First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2′ of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
摘要翻译： 形成第一和第二栅极绝缘膜，以至少覆盖第一和第二鳍状半导体区域的上角。 位于第一栅极绝缘膜外侧的第一鳍状半导体区域的上角的曲率半径r1'大于位于第一栅极下方的第一鳍状半导体区域的上角的曲率半径r1 绝缘膜，小于或等于2×r1。 位于第二栅极绝缘膜外侧的第二鳍状半导体区域的上角的曲率半径r2'大于位于第二栅极下方的第二鳍状半导体区域的上角的曲率半径r2 绝缘膜，小于或等于2×r2。
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公开(公告)号：US20090289300A1
公开(公告)日：2009-11-26
申请号：US12512617
申请日：2009-07-30
IPC分类号： H01L29/78 , H01L27/092 , H01L21/8238
CPC分类号： H01L29/66803 , H01L29/66795 , H01L29/7854
摘要： First and second gate insulating films are formed so as to cover at least the upper corner of first and second fin-shaped semiconductor regions. The radius of curvature r1′ of the upper corner of the first fin-shaped semiconductor region located outside the first gate insulating film is greater than the radius of curvature r1 of the upper corner of the first fin-shaped semiconductor region located under the first gate insulating film and is less than or equal to 2×r1. The radius of curvature r2′ of the upper corner of the second fin-shaped semiconductor region located outside the second gate insulating film is greater than the radius of curvature r2 of the upper corner of the second fin-shaped semiconductor region located under the second gate insulating film and is less than or equal to 2×r2.
摘要翻译： 第一和第二栅极绝缘膜形成为至少覆盖第一和第二鳍状半导体区域的上角。 位于第一栅极绝缘膜外侧的第一鳍状半导体区域的上角的曲率半径r1'大于位于第一栅极下方的第一鳍状半导体区域的上角的曲率半径r1 绝缘膜，小于或等于2×r1。 位于第二栅极绝缘膜外侧的第二鳍状半导体区域的上角的曲率半径r2'大于位于第二栅极下方的第二鳍状半导体区域的上角的曲率半径r2 绝缘膜，小于或等于2×2。
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公开(公告)号：US20080318399A1
公开(公告)日：2008-12-25
申请号：US12139968
申请日：2008-06-16
IPC分类号： H01L21/26
CPC分类号： H01L21/2236 , H01J37/32412 , H01L29/66795
摘要： A plasma doping method that can control a dose precisely is realized. In-plane uniformity of the dose is improved.It has been found that, if a bias is applied by irradiating B2H6/He plasma onto a silicon substrate, there is a time at which a dose of boron is made substantially uniform, and the saturation time is comparatively long and ease to stably use, compared with a time at which repeatability of an apparatus control can be secured. The invention has been finalized focusing on the result. That is, if plasma irradiation starts, a dose is initially increased, but a time at which the dose is made substantially uniform without depending on a time variation is continued. In addition, if the time is further increased, the dose is decreased. The dose can be accurately controlled through a process window of the time at which the dose is made substantially uniform without depending on the time variation.
摘要翻译： 实现了可以精确控制剂量的等离子体掺杂方法。 剂量的面内均匀性得到改善。 已经发现，如果通过将B2H6 / He等离子体照射到硅衬底上施加偏压，则存在使硼剂量基本均匀的时间，并且饱和时间比较长并且易于稳定使用， 与可以确保装置控制的可重复性的时间相比。 本发明已经确定了结果。 也就是说，如果等离子体照射开始，则剂量最初增加，但是持续施加剂量基本上均匀而不依赖于时间变化的时间。 此外，如果时间进一步增加，则剂量降低。 剂量可以通过在剂量基本均匀的时间的过程窗口中被准确地控制，而不依赖于时间变化。
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公开(公告)号：US20120119295A1
公开(公告)日：2012-05-17
申请号：US13356346
申请日：2012-01-23
申请人： Yuichiro SASAKI , Katsumi Okashita , Bunji Mizuno
发明人： Yuichiro SASAKI , Katsumi Okashita , Bunji Mizuno
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： A fin-type semiconductor region (103) is formed on a substrate (101), and then a resist pattern (105) is formed on the substrate (101). An impurity is implanted into the fin-type semiconductor region (103) by a plasma doping process using the resist pattern (105) as a mask, and then at least a side of the fin-type semiconductor region (103) is covered with a protective film (107). Thereafter, the resist pattern (105) is removed by cleaning using a chemical solution, and then the impurity implanted into the fin-type semiconductor region (103) is activated by heat treatment.
摘要翻译： 在基板（101）上形成翅片型半导体区域（103），然后在基板（101）上形成抗蚀图案（105）。 通过使用抗蚀剂图案（105）作为掩模的等离子体掺杂工艺将杂质注入到鳍式半导体区域（103）中，然后用鳍状半导体区域（103）的至少一侧覆盖 保护膜（107）。 此后，通过使用化学溶液的清洗除去抗蚀剂图案（105），然后通过热处理激活注入到鳍式半导体区域（103）中的杂质。
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8.发明申请公开(公告)号：US20110237056A1
公开(公告)日：2011-09-29
申请号：US13155175
申请日：2011-06-07
申请人： Yuichiro SASAKI , Cheng-Guo JIN , Bunji MIZUNO
发明人： Yuichiro SASAKI , Cheng-Guo JIN , Bunji MIZUNO
IPC分类号： H01L21/265
CPC分类号： H01L21/268
摘要： An object of this invention is to provide a method for making a junction which is simple in the process, high in the throughput, and can make a shallow junction with high accuracy. After the suitable state of a substrate surface adapted to the wavelength of an electromagnetic wave to be applied has been formed, the electromagnetic wave is applied to electrically activate impurities so that the excited energy is effectively absorbed within the impurity thin film, thereby effectively making a shallow junction.
摘要翻译： 本发明的目的是提供一种制造接头的方法，其工艺简单，生产能力高，并且可以以高精度形成浅结。 在形成适合于要施加的电磁波的波长的基板表面的合适状态之后，施加电磁波以电激活杂质，使得激发能量被有效地吸收在杂质薄膜内，从而有效地使 浅交界处
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9.发明申请公开(公告)号：US20080160728A1
公开(公告)日：2008-07-03
申请号：US12040476
申请日：2008-02-29
申请人： Yuichiro SASAKI , Bunji Mizuno , Cheng-Guo Jin
发明人： Yuichiro SASAKI , Bunji Mizuno , Cheng-Guo Jin
IPC分类号： H01L21/265
CPC分类号： H01L21/26506 , H01L21/223 , H01L21/2236 , H01L21/2254 , Y10T117/10
摘要： A method for introducing impurities includes a step for forming an amorphous layer at a surface of a semiconductor substrate, and a step for forming a shallow impurity-introducing layer at the semiconductor substrate which has been made amorphous, and an apparatus used therefore. Particularly, the step for forming the amorphous layer is a step for irradiating plasma to the surface of the semiconductor substrate, and the step for forming the shallow impurity-introducing layer is a step for introducing impurities into the surface which has been made amorphous.
摘要翻译： 用于引入杂质的方法包括在半导体衬底的表面形成非晶层的步骤，以及在半导体衬底上形成非晶化的浅杂质引入层的步骤以及因此使用的装置。 特别地，用于形成非晶层的步骤是用于将等离子体照射到半导体衬底的表面的步骤，并且用于形成浅掺杂杂质的层的步骤是将杂质引入已经被制成无定形的表面的步骤。
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公开(公告)号：US20130022759A1
公开(公告)日：2013-01-24
申请号：US13611939
申请日：2012-09-12
IPC分类号： C23C16/50
CPC分类号： H01J37/3244 , H01J37/32412 , H01L21/2236
摘要： With the evacuation of an interior of a vacuum chamber halted and with gas supply into the vacuum chamber halted, in a state that a mixed gas of helium gas and diborane gas is sealed in the vacuum chamber, a plasma is generated in a vacuum vessel and simultaneously a high-frequency power is supplied to a sample electrode. By the high-frequency power supplied to the sample electrode, boron is introduced to a proximity to a substrate surface.
摘要翻译： 随着真空室内部的抽真空，并且气体供应到真空室中停止，在氦气和乙硼烷气体的混合气体被密封在真空室中的状态下，在真空容器中产生等离子体， 同时向样品电极提供高频电力。 通过提供给样品电极的高频电力，将硼引入到衬底表面附近。
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