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13 条记录 (耗时 0.031 秒)

    Packet-data processing apparatus
    1.
    发明授权
    Packet-data processing apparatus 失效
    分组数据处理装置

    公开(公告)号：US06654823B2

    公开(公告)日：2003-11-25

    申请号：US09818354

    申请日：2001-03-27

    申请人： Satoshi Soejima ,  Yuji Kojima ,  Yasuyuki Umezaki ,  Tetsumei Tsuruoka ,  Yoshitomo Shimozono

    发明人： Satoshi Soejima ,  Yuji Kojima ,  Yasuyuki Umezaki ,  Tetsumei Tsuruoka ,  Yoshitomo Shimozono

    IPC分类号： G06F300

    CPC分类号： H04L12/4633

    摘要： A packet-data-processing apparatus includes a first data-processing unit for computing information on a processing count; a memory; a second data-processing-unit for processing the input packet and storing first results in the memory; an access mechanism unit for reading out one of the first results written into the memory least recently from the memory at a request for a read operation and deleting the result of processing read out from the memory; a third data-processing unit for making the request for a read operation and carrying out processing based on the first result read out by the access control unit at the request and an input packet associated with the result of processing; and fourth data-processing unit constituting pipeline data-processing mechanism with the first and third data-processing unit.

    摘要翻译： 分组数据处理装置包括用于计算关于处理计数的信息的第一数据处理单元; 记忆 第二数据处理单元，用于处理输入分组并将第一结果存储在存储器中; 访问机构单元，用于在请求读取操作时从存储器中最少读出写入存储器的第一结果中的一个，并从存储器中删除从该存储器读出的处理结果; 第三数据处理单元，用于基于由访问控制单元根据请求读出的第一结果和与处理结果相关联的输入分组进行读操作请求和执行处理; 以及与第一和第三数据处理单元构成流水线数据处理机构的第四数据处理单元。

    Packet processor
    2.
    发明授权
    Packet processor 失效
    分组处理器

    公开(公告)号：US06799267B2

    公开(公告)日：2004-09-28

    申请号：US09742939

    申请日：2000-12-20

    申请人： Yuji Kojima ,  Tetsumei Tsuruoka ,  Kenichi Abiru ,  Yasuyuki Umezaki ,  Yoshitomo Shimozono

    发明人： Yuji Kojima ,  Tetsumei Tsuruoka ,  Kenichi Abiru ,  Yasuyuki Umezaki ,  Yoshitomo Shimozono

    IPC分类号： G06F9302

    CPC分类号： G06F9/3885 ,  G06F9/30018 ,  G06F9/30032

    摘要： A packet processor having a general-purpose arithmetic operator and another dedicated circuit, which extracts a particular field from the general-purpose register as object field, on which the predetermined general-purpose arithmetic operation is to be performed by the general-purpose arithmetic operator and writes a result of the arithmetic operation by the general-purpose arithmetic operator into the general-purpose register as updated information of the particular field. Based on the extraction and write process of the packet field designated by software (instructions), the packet processor realizes high flexibility and high speed processing.

    摘要翻译： 具有通用算术运算器和另一专用电路的分组处理器，其从通用寄存器中提取特定字段作为对象字段，由通用算术运算符执行预定的通用算术运算 并将通用算术运算器的算术运算结果写入通用寄存器作为特定字段的更新信息。 基于由软件（指令）指定的分组字段的提取和写入过程，分组处理器实现高灵活性和高速处理。

    Speed converting apparatus with load controlling function and information processing system
    10.
    发明申请
    Speed converting apparatus with load controlling function and information processing system 有权
    具有负载控制功能和信息处理系统的速度转换装置

    公开(公告)号：US20060212285A1

    公开(公告)日：2006-09-21

    申请号：US11153419

    申请日：2005-06-16

    申请人： Minoru Kawarabayashi ,  Takayuki Shimamura ,  Tatekuni Onoue ,  Yasuyuki Umezaki

    发明人： Minoru Kawarabayashi ,  Takayuki Shimamura ,  Tatekuni Onoue ,  Yasuyuki Umezaki

    IPC分类号： G06F9/455

    CPC分类号： G06F11/261

    摘要： A speed converting apparatus with a load controlling function comprises a first interface unit operating for an emulation device according to a system clock of the emulation device, a second interface unit operating for an arithmetic unit according to a system clock of the arithmetic unit, and a load controlling unit controlling at least either a load of a request outputted to the emulation device on the emulation device or a load of a request outputted to the arithmetic unit on the arithmetic unit. In performance verification or connection verification of a target to be verified, the speed converting apparatus can vary a load of a request issued to the target to be verified on the target or a load issued to a verification device on the verification device, while absorbing a difference in operation speed between the target to be verified and the verification device.

    摘要翻译： 具有负载控制功能的速度转换装置包括根据仿真装置的系统时钟为仿真装置操作的第一接口单元，根据运算单元的系统时钟对运算单元运行的第二接口单元，以及 负载控制单元至少控制在仿真装置上输出到仿真装置的请求的负载或者在运算单元上输出到运算单元的请求的负载。 在要验证的目标的性能验证或连接验证中，速度转换装置可以在发送给目标上的目标的请求的负载或发送给验证装置上的验证装置的负载上，同时吸收 待验证目标与验证装置之间的运行速度差。