公开(公告)号：US5309045A

公开(公告)日：1994-05-03

申请号：US880591

申请日：1992-05-08

申请人： Yukihiro Saeki ,  Hiroki Muroga ,  Tomohisa Shigematsu ,  Toshio Hibi ,  Yasuo Kawahara ,  Kazunao Maru ,  Kenneth Austin ,  Gordon S. Work ,  Darren M. Wedgwood

发明人： Yukihiro Saeki ,  Hiroki Muroga ,  Tomohisa Shigematsu ,  Toshio Hibi ,  Yasuo Kawahara ,  Kazunao Maru ,  Kenneth Austin ,  Gordon S. Work ,  Darren M. Wedgwood

IPC分类号： G11C11/404 ,  G11C11/412 ,  H03K19/177 ,  H03K19/096

CPC分类号： H03K19/17764 ,  G11C11/404 ,  G11C11/412 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774

摘要： A programmable logic unit circuit comprising a data memory circuit, a combinational logic circuit supplied with at least two input signals, two input select circuits for, based on the stored data in the data memory circuit, selecting the two input signals supplied to the combinational logic circuit from more than two input signals, a clock-synchronized circuit for supplying the output signal from the combinational logic circuit in synchronization with a clock signal, and a 3-state-output type output select circuit for selecting either the output signal of the combinational logic circuit or the output signal of the clock-synchronized circuit, depending on the stored data in the data memory circuit.

摘要翻译： 一种可编程逻辑单元电路，包括数据存储器电路，提供有至少两个输入信号的组合逻辑电路，基于数据存储电路中存储的数据的两个输入选择电路，选择提供给组合逻辑的两个输入信号 来自多于两个输入信号的电路，用于从组合逻辑电路提供与时钟信号同步的输出信号的时钟同步电路，以及用于选择组合的输出信号的3态输出型输出选择电路 逻辑电路或时钟同步电路的输出信号，这取决于数据存储电路中存储的数据。

公开(公告)号：US5163023A

公开(公告)日：1992-11-10

申请号：US602369

申请日：1990-10-23

申请人： Andrew T. Ferris ,  Gordon S. Work

发明人： Andrew T. Ferris ,  Gordon S. Work

IPC分类号： G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/848

摘要： A memory circuit comprises a memory array having a plurality of memory cells arranged in rows and columns. Column select circuits enable access to the columns in the array. Each column select circuit is associated with a respective group of the columns and is arranged to access a selected one of the columns in the respective group. At least one spare memory column is provided. Also included are a plurality of read/write circuits associated respectively with the groups, and with the spare memory column, for reading or writing data bits between a data bus and the columns selected by the column selected circuits. Routing circuitry is connected between the read/write circuits and the data bus and is programmable with information identifying at least one faulty column. The routing circuitry is operable in response to an attempted access to the faulty column by disconnecting from the data bus the read/write circuit associated with the group containing the faulty column and connecting to the data bus the read/write circuit associated with the spare column thereby to transfer data between the spare column and the data bus.

公开(公告)号：US5268869A

公开(公告)日：1993-12-07

申请号：US596200

申请日：1990-10-11

申请人： Andrew T. Ferris ,  Gordon S. Work

发明人： Andrew T. Ferris ,  Gordon S. Work

IPC分类号： G11C11/407 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C11/413 ,  G11C11/417 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/14 ,  Y10S438/926

摘要： A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common wordline (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell. A plurality of said dummy cells (22) has a bit value stored therein and is connected to a dummy wordline and the remainder of said dummy cells are rendered inactive, whereby on addressing of the dummy wordline simultaneously with the wordline of an accessed cell, a predetermined number of dummy cells discharges via the dummy bit line so that the voltage developed on the dummy bit line bears a predetermined relationship to the voltage differential developed between the bit lines of the accessed cell. The timing circuit (16) is connected to receive the voltage differential on the dummy bit line (18).

公开(公告)号：US5379382A

公开(公告)日：1995-01-03

申请号：US871518

申请日：1992-04-21

申请人： Gordon S. Work ,  Gareth J. Jones ,  Peter A. Albiez

发明人： Gordon S. Work ,  Gareth J. Jones ,  Peter A. Albiez

IPC分类号： G06F13/38 ,  G06F13/00

CPC分类号： G06F13/385

摘要： A peripheral controller is described which is suitable for connecting a selected one of a plurality of peripheral devices to a computer system. The peripheral controller comprises programmable bidirectional line driver/receiver devices which can be operated in an input only mode, an output only mode or a bidirectional mode and which can be set into an appropriate mode by configuration control data sent from the computer system to the peripheral controller. The peripheral controller also includes a re-configurable logic array which can be configured under the control of the configuration control data to implement a particular interface required for the selected peripheral device. This increases the efficiency of use of a peripheral interface.

摘要翻译： 描述了外围控制器，其适于将多个外围设备中的所选择的一个连接到计算机系统。 外围控制器包括可编程双向线路驱动器/接收机设备，其可以仅在输入模式，仅输出模式或双向模式下操作，并且可以通过从计算机系统发送到外围设备的配置控制数据将其设置为适当的模式 控制器。 外围控制器还包括可配置逻辑阵列，其可以在配置控制数据的控制下配置，以实现所选择的外围设备所需的特定接口。 这增加了外围接口的使用效率。

公开(公告)号：US4769632A

公开(公告)日：1988-09-06

申请号：US828208

申请日：1986-02-10

申请人： Gordon S. Work ,  Gerald R. Talbot

发明人： Gordon S. Work ,  Gerald R. Talbot

IPC分类号： G09G5/02 ,  G09G1/28 ,  G09G5/06 ,  H03M1/68

CPC分类号： G09G5/06

摘要： A color graphics control system for generating red, blue and green analog signals to a raster scan display at a pixel frequency comprises a RAM storing a pluraltiy of digital color values, digital to analog converters for converting the digital color values into analog signals, an interface to permit an external controller to write digital color values into the RAM locations, a timer including a pixel clock and RAM accessing means controlled by the timer to pipeline RAM accessing with a cycle time of more than one pixel period.

摘要翻译： 用于以像素频率向光栅扫描显示产生红色，蓝色和绿色模拟信号的彩色图形控制系统包括存储多个数字颜色值的RAM，用于将数字颜色值转换为模拟信号的数模转换器，接口 允许外部控制器将数字颜色值写入RAM位置，定时器包括由定时器控制的像素时钟和RAM存取装置，以便以多于一个像素周期的周期时间流水线RAM访问。