公开(公告)号：US07043597B2

公开(公告)日：2006-05-09

申请号：US10605030

申请日：2003-09-03

申请人： Yung-Chun Lei ,  Chun-Nan Lin

发明人： Yung-Chun Lei ,  Chun-Nan Lin

IPC分类号： G06F12/00

CPC分类号： G06F8/65

摘要： The processing system is electrically connected to a computer and has a non-volatile memory (NVM) for storing firmware and an NVM control interface having a plurality of registers for updating and reading data stored in the NVM. When the NVM control interface updates a current piece of data stored in the NVM, the NVM control interface first reads a prior piece of data that is stored in the NVM prior to the current piece of data and transmits the prior piece of data to the computer for comparison, then the NVM control interface updates the current piece of data.

摘要翻译： 处理系统电连接到计算机，并具有用于存储固件的非易失性存储器（NVM）和具有用于更新和读取存储在NVM中的数据的多个寄存器的NVM控制接口。 当NVM控制接口更新存储在NVM中的当前数据时，NVM控制接口首先在当前数据之前读取存储在NVM中的先前数据，并将先前的数据发送到计算机 为了进行比较，NVM控制界面更新了当前的数据。

公开(公告)号：US07251706B2

公开(公告)日：2007-07-31

申请号：US11308243

申请日：2006-03-14

申请人： Yung-Chun Lei ,  Chun-Nan Lin

发明人： Yung-Chun Lei ,  Chun-Nan Lin

IPC分类号： G06F12/00

CPC分类号： G06F8/65

摘要： A processing system connected to an apparatus includes a non-volatile memory (NVM) for storing firmware needed by the processing system; and an NVM control interface capable of writing and reading data stored in the NVM; wherein the NVM control interface reads a previous piece of data being already written into the NVM prior to a current piece of data and transmits the previous piece of data to the apparatus for comparison with original data that was previously written into the NVM, and the NVM control interface writes the current piece of data into the NVM.

摘要翻译： 连接到装置的处理系统包括用于存储处理系统所需的固件的非易失性存储器（NVM） 以及能够写入和读取存储在NVM中的数据的NVM控制接口; 其中NVM控制接口在当前数据片段之前读取已经写入NVM中的先前数据块，并将先前的数据发送到装置以便与先前写入NVM的原始数据进行比较，并且NVM 控制接口将当前数据写入NVM。

公开(公告)号：US20060184763A1

公开(公告)日：2006-08-17

申请号：US11308243

申请日：2006-03-14

申请人： Yung-Chun Lei ,  Chun-Nan Lin

发明人： Yung-Chun Lei ,  Chun-Nan Lin

IPC分类号： G06F9/34

CPC分类号： G06F8/65

摘要： A processing system connected to an apparatus includes a non-volatile memory (NVM) for storing firmware needed by the processing system; and an NVM control interface capable of writing and reading data stored in the NVM; wherein the NVM control interface reads a previous piece of data being already written into the NVM prior to a current piece of data and transmits the previous piece of data to the apparatus for comparison with original data that was previously written into the NVM, and the NVM control interface writes the current piece of data into the NVM.

摘要翻译： 连接到装置的处理系统包括用于存储处理系统所需的固件的非易失性存储器（NVM） 以及能够写入和读取存储在NVM中的数据的NVM控制接口; 其中NVM控制接口在当前数据片段之前读取已经写入NVM的先前数据块，并将先前的数据发送到装置以与之前写入NVM的原始数据进行比较，并且NVM 控制接口将当前数据写入NVM。

公开(公告)号：US07490194B2

公开(公告)日：2009-02-10

申请号：US11772237

申请日：2007-07-01

申请人： Yung-Chun Lei ,  Chun-Nan Lin

发明人： Yung-Chun Lei ,  Chun-Nan Lin

IPC分类号： G06F12/00

CPC分类号： G06F8/65

摘要： A processing system coupled to an apparatus is provided. The processing system includes: a non-volatile memory (NVM) storing firmware needed by the processing system; and an NVM control interface writing and reading data stored in the NVM. The apparatus verifies a previous piece of data being already written into the NVM, and the NVM control interface writes a current piece of data into the NVM.

摘要翻译： 提供耦合到装置的处理系统。 处理系统包括：存储由处理系统所需的固件的非易失性存储器（NVM）; 以及一个NVM控制接口，写入和读取存储在NVM中的数据。 该装置验证先前已经写入NVM的数据，NVM控制接口将当前数据写入NVM。

公开(公告)号：US20080016268A1

公开(公告)日：2008-01-17

申请号：US11772237

申请日：2007-07-01

申请人： Yung-Chun Lei ,  Chun-Nan Lin

发明人： Yung-Chun Lei ,  Chun-Nan Lin

IPC分类号： G06F12/00

CPC分类号： G06F8/65

摘要： A processing system coupled to an apparatus is provided. The processing system includes: a non-volatile memory (NVM) storing firmware needed by the processing system; and an NVM control interface writing and reading data stored in the NVM. The apparatus verifies a previous piece of data being already written into the NVM, and the NVM control interface writes a current piece of data into the NVM.

摘要翻译： 提供耦合到装置的处理系统。 处理系统包括：存储由处理系统所需的固件的非易失性存储器（NVM）; 以及一个NVM控制接口，写入和读取存储在NVM中的数据。 该装置验证先前已经写入NVM的数据，NVM控制接口将当前数据写入NVM。

公开(公告)号：US20060210088A1

公开(公告)日：2006-09-21

申请号：US11081510

申请日：2005-03-17

申请人： Yung-Chun Lei ,  Tzueng-yau Lin

发明人： Yung-Chun Lei ,  Tzueng-yau Lin

IPC分类号： H04R5/00 ,  G06F17/00

CPC分类号： H04B1/0014 ,  H04L27/0014 ,  H04N5/4446 ,  H04N5/607

摘要： The invention discloses a decoding apparatus for decoding an analog audio signal. The decoding apparatus includes an RF tuner, an analog to digital (A/D) converter, a digital down converter, and a programmable digital signal processor (DSP). The RF tuner is used for receiving the analog audio signal and for providing an analog sound intercarrier frequency (SIF) signal indicative thereof. The analog to digital (A/D) converter is used for sampling the analog SIF signal and for converting the signal into a digital SIF signal. The digital down converter is used for down converting the digital SIF signal to generate a baseband signal. The programmable digital signal processor (DSP) is used for demodulating the baseband signal according to a demodulation procedure of a predetermined standard and decoding the demodulated baseband signal to output an output signal in compliance with a decoding procedure of the predetermined standard.

摘要翻译： 本发明公开了一种解码模拟音频信号的解码装置。 解码装置包括RF调谐器，模数（A / D）转换器，数字下变频器和可编程数字信号处理器（DSP）。 RF调谐器用于接收模拟音频信号并用于提供指示其的模拟声音载波间频率（SIF）信号。 模数（A / D）转换器用于对模拟SIF信号进行采样，并将信号转换为数字SIF信号。 数字下变频器用于下变频数字SIF信号以产生基带信号。 可编程数字信号处理器（DSP）用于根据预定标准的解调程序对基带信号进行解调，并对解调的基带信号进行解码，以根据预定标准的解码过程输出输出信号。

公开(公告)号：US07853021B2

公开(公告)日：2010-12-14

申请号：US11081510

申请日：2005-03-17

申请人： Yung-Chun Lei ,  Tzueng-yau Lin

发明人： Yung-Chun Lei ,  Tzueng-yau Lin

IPC分类号： H04H20/47 ,  H04H20/88 ,  H04H40/36

CPC分类号： H04B1/0014 ,  H04L27/0014 ,  H04N5/4446 ,  H04N5/607

摘要： The invention discloses a decoding apparatus for decoding an analog audio signal. The decoding apparatus includes an RF tuner, an analog to digital (A/D) converter, a digital down converter, and a programmable digital signal processor (DSP). The RF tuner is used for receiving the analog audio signal and for providing an analog sound intercarrier frequency (SIF) signal indicative thereof. The analog to digital (A/D) converter is used for sampling the analog SIF signal and for converting the signal into a digital SIF signal. The digital down converter is used for down converting the digital SIF signal to generate a baseband signal. The programmable digital signal processor (DSP) is used for demodulating the baseband signal according to a demodulation procedure of a predetermined standard and decoding the demodulated baseband signal to output an output signal in compliance with a decoding procedure of the predetermined standard.

摘要翻译： 本发明公开了一种解码模拟音频信号的解码装置。 解码装置包括RF调谐器，模数（A / D）转换器，数字下变频器和可编程数字信号处理器（DSP）。 RF调谐器用于接收模拟音频信号并用于提供指示其的模拟声音载波间频率（SIF）信号。 模数（A / D）转换器用于对模拟SIF信号进行采样，并将信号转换为数字SIF信号。 数字下变频器用于下变频数字SIF信号以产生基带信号。 可编程数字信号处理器（DSP）用于根据预定标准的解调程序对基带信号进行解调，并对解调的基带信号进行解码，以根据预定标准的解码过程输出输出信号。

公开(公告)号：US20090082886A1

公开(公告)日：2009-03-26

申请号：US11859169

申请日：2007-09-21

申请人： Yung-Chun Lei ,  Shang-Tzu Ju

发明人： Yung-Chun Lei ,  Shang-Tzu Ju

IPC分类号： G06F17/00

CPC分类号： H04B1/1646 ,  G11B20/10037 ,  G11B20/10527 ,  G11B20/1415 ,  G11B2020/10546 ,  H04S1/007

摘要： An audio system and an audio processing method are provided. The audio system comprises a down mixer, an ADC, a storage unit, a control unit, a DSP unit, and a DAC. The down mixer first down-converts an analog signal, which is then converted by the ADC into a first audio digital signal. The storage unit stores a second audio digital signal. The control unit generates a control signal. The DSP unit then processes the first audio digital signal or the second audio digital signal according to the control signal to generate a processed audio digital signal. The DAC converts this processed audio digital signal to a processed analog signal for playback. The audio processing method comprises the steps executed in the audio system.

摘要翻译： 提供音频系统和音频处理方法。 音频系统包括下混频器，ADC，存储单元，控制单元，DSP单元和DAC。 下混频器首先对模拟信号进行下变频，然后模拟信号由ADC转换成第一音频数字信号。 存储单元存储第二音频数字信号。 控制单元生成控制信号。 然后，DSP单元根据控制信号处理第一音频数字信号或第二音频数字信号，以产生经处理的音频数字信号。 DAC将该处理后的音频数字信号转换为已处理的模拟信号进行播放。 音频处理方法包括在音频系统中执行的步骤。

公开(公告)号：US20050010632A1

公开(公告)日：2005-01-13

申请号：US10710398

申请日：2004-07-08

申请人： Yung-Chun Lei ,  Yu-Chu Chen ,  Yu-Chi Chang

发明人： Yung-Chun Lei ,  Yu-Chu Chen ,  Yu-Chi Chang

IPC分类号： G06F7/38 ,  G06F7/48 ,  G06F7/523 ,  G06F7/544 ,  G06F15/76 ,  H03M7/24

CPC分类号： G06F7/48 ,  G06F7/523 ,  G06F7/5443 ,  G06F2207/3816 ,  G06F2207/3824 ,  H03M7/24

摘要： A digital signal processor for processing a plurality of digital data in a fixed-point representation or a jumping floating-point representation. The digital signal processor includes a multiplication circuit, an extracting/shifting device, a plurality of representation converters, and an arithmetic unit. The multiplication circuit is used to generate a long bit-length digital data by multiplying two short bit-length digital data with each other. The extracting/shifting device is electrically connected to the multiplication circuit for transforming the long bit-length digital data in jumping floating-point representation to a long bit-length digital data in fixed-point representation. Each representation converter is used to transform a digital data between the fixed-point representation and the jumping floating-point representation. The arithmetic unit is used to operate a plurality of digital data.

摘要翻译： 一种用于以固定点表示或跳跃浮点表示来处理多个数字数据的数字信号处理器。 数字信号处理器包括乘法电路，提取/移位装置，多个表示转换器和运算单元。 乘法电路用于通过将两个短位长数字数据彼此相乘来产生长位数字数据。 提取/移位装置电连接到乘法电路，用于将跳跃浮点表示中的长位数字数据变换为定点表示中的长位数字数据。 每个表示转换器用于在定点表示和跳跃浮点表示之间转换数字数据。 算术单元用于操作多个数字数据。

公开(公告)号：US07555678B2

公开(公告)日：2009-06-30

申请号：US11277349

申请日：2006-03-23

申请人： Ming-Shiang Lai ,  Yung-Chun Lei

发明人： Ming-Shiang Lai ,  Yung-Chun Lei

IPC分类号： G06F11/00

CPC分类号： G06F9/4406 ,  G06F9/4403 ,  G06F9/44573 ,  G06F11/1417 ,  G06F11/1658

摘要： A booting system is disclosed for booting from a non-XIP memory utilizing a boot engine that does not have ECC capabilities during booting. The booting system includes: a non-XIP memory for storing a boot loader code and a plurality of operation system (OS) images, wherein the OS images in the non-XIP memory correspond to a same source image; an XIP memory for storing a shadowed boot loader code and OS images; a Central Processing Unit (CPU) for executing the OS images stored in the XIP memory; a code shadowing module for performing error detection checking on the OS images in the non-XIP memory and shadowing the boot loader code and OS images to the XIP memory; and a non-XIP interface for enabling the boot engine to access the non-XIP memory.

摘要翻译： 公开了一种引导系统，用于使用在引导期间不具有ECC能力的引导引擎从非XIP存储器引导。 引导系统包括：用于存储引导加载程序代码和多个操作系统（OS）图像的非XIP存储器，其中非XIP存储器中的OS图像对应于相同的源图像; 用于存储被遮罩的引导加载器代码和OS映像的XIP存储器; 用于执行存储在XIP存储器中的OS图像的中央处理单元（CPU）; 代码阴影模块，用于对非XIP存储器中的OS映像执行错误检测检查，并将引导加载程序代码和OS映像映射到XIP存储器; 以及用于使引导引擎访问非XIP存储器的非XIP接口。