公开(公告)号：US06291306B1

公开(公告)日：2001-09-18

申请号：US09357243

申请日：1999-07-19

申请人： Yung-Lung Hsu ,  Shun-Liang Hsu ,  Yean-Kuen Fang ,  Mao-Hsiung Kuo

发明人： Yung-Lung Hsu ,  Shun-Liang Hsu ,  Yean-Kuen Fang ,  Mao-Hsiung Kuo

IPC分类号： H01L2120

CPC分类号： H01L28/20 ,  H01L27/0802

摘要： A method of forming a high polysilicon resistor over a dielectric layer, comprising the following steps. A polysilicon resistor over a semiconductor structure is provided. The polysilicon resistor has a doped polysilicon layer having a first voltage coefficient of resistance and grain boundaries having a first trapping density. A to a first level of DC current is provided for a predetermined duration through the doped polysilicon layer to stress the doped polysilicon layer to partially melt the doped polysilicon layer without causing breakdown of the doped polysilicon layer. The to a first level of DC current is removed to allow recrystallization of the melted doped polysilicon layer, whereby the recrystallized doped polysilicon layer has a second voltage coefficient of resistance less than the first voltage coefficient of resistance and grain boundaries having a second trapping density that is less than the first trapping density. This makes the Rs of the polysilicon to be stable and saturated.

摘要翻译： 一种在电介质层上形成高多晶硅电阻的方法，包括以下步骤。 提供了半导体结构上的多晶硅电阻器。 多晶硅电阻器具有掺杂多晶硅层，其具有第一电压电阻系数和具有第一捕获密度的晶界。 通过掺杂多晶硅层将A到第一级DC电流提供预定持续时间，以施加掺杂多晶硅层以部分地熔化掺杂多晶硅层而不引起掺杂多晶硅层的击穿。 除去第一级直流电流以允许熔融掺杂多晶硅层重结晶，由此再结晶掺杂多晶硅层具有小于第一电压系数电阻的第二电压系数和具有第二陷阱密度的晶界， 小于第一个捕获密度。 这使得多晶硅的Rs稳定和饱和。

公开(公告)号：US20070194830A1

公开(公告)日：2007-08-23

申请号：US11356707

申请日：2006-02-17

申请人： Mao-Hsiung Kuo

发明人： Mao-Hsiung Kuo

IPC分类号： H03L5/00

CPC分类号： H03K3/012 ,  H03K3/356165

摘要： A level shift circuit adds two NMOS transistors or two PMOS transistors between the NMOS transistors and PMOS transistors at the VP-side and the VN-side and connects the gates of the added transistors to the two output terminals. By this architecture, the level shift circuit of the present invention can successfully convert a small input voltage into a large output voltage with less DC current and/or without any additional bandgap circuit.

摘要翻译： 电平移位电路在VP侧和VN侧的NMOS晶体管和PMOS晶体管之间添加两个NMOS晶体管或两个PMOS晶体管，并将所加入的晶体管的栅极连接到两个输出端子。 通过这种架构，本发明的电平移位电路可以以较小的DC电流和/或没有任何附加的带隙电路成功地将小的输入电压转换成大的输出电压。

公开(公告)号：US08669974B2

公开(公告)日：2014-03-11

申请号：US11808828

申请日：2007-06-13

申请人： Yu-Chu Yang ,  Fa-Ming Chen ,  Po-Hsien Tsai ,  Mao-Hsiung Kuo

发明人： Yu-Chu Yang ,  Fa-Ming Chen ,  Po-Hsien Tsai ,  Mao-Hsiung Kuo

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/2092 ,  G09G2320/0257 ,  G09G2330/027

摘要： A timing controller adapted to a flat display includes a voltage detecting circuit, a clock generator, a first multiplexer and a second multiplexer. The voltage detecting circuit detects a variation of an operating voltage and thus outputs a reset signal. The clock generator outputs a start signal and a first clock signal. The first multiplexer is controlled by the reset signal and coupled to the start signal and a constant voltage. The second multiplexer is controlled by the reset signal and coupled to the first clock signal and a second clock signal. A frequency of the second clock signal is obviously higher than a frequency of the first clock signal.

摘要翻译： 适于平面显示器的定时控制器包括电压检测电路，时钟发生器，第一多路复用器和第二多路复用器。 电压检测电路检测工作电压的变化，从而输出复位信号。 时钟发生器输出起始信号和第一时钟信号。 第一复用器由复位信号控制并耦合到起始信号和恒定电压。 第二复用器由复位信号控制并耦合到第一时钟信号和第二时钟信号。 第二时钟信号的频率明显高于第一时钟信号的频率。

公开(公告)号：US08044913B2

公开(公告)日：2011-10-25

申请号：US11833840

申请日：2007-08-03

申请人： Mao-Hsiung Kuo ,  Chien-Pin Chen ,  Fa-Ming Chen

发明人： Mao-Hsiung Kuo ,  Chien-Pin Chen ,  Fa-Ming Chen

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0443 ,  G09G2310/0289 ,  G09G2310/06

摘要： A gate driver for driving a display device is disclosed. The gate driver, which includes: a first input buffer configured to for receiving a reference voltage and outputting a first buffered voltage, a control circuit configured to for outputting a plurality of scan starting signals and compensating starting signals, a plurality of compensating output buffers, and a plurality of scan output buffers. Each of the plurality of compensating output buffers is configured to respectively receive one of the compensating starting signals and respectively output a compensating signal, wherein, each compensating output buffer receives the first buffered voltage as power. Each of the plurality of scanning output buffers is configured to respectively receive one of the scan starting signals and output a scan signal.

摘要翻译： 公开了用于驱动显示装置的栅极驱动器。 所述栅极驱动器包括：第一输入缓冲器，被配置为用于接收参考电压并输出第一缓冲电压;控制电路，被配置为输出多个扫描启动信号和补偿启动信号，多个补偿输出缓冲器， 和多个扫描输出缓冲器。 多个补偿输出缓冲器中的每一个被配置为分别接收补偿起始信号之一并分别输出补偿信号，其中每个补偿输出缓冲器接收第一缓冲电压作为功率。 多个扫描输出缓冲器中的每一个被配置为分别接收扫描起始信号之一并输出扫描信号。

公开(公告)号：US20080231582A1

公开(公告)日：2008-09-25

申请号：US11833840

申请日：2007-08-03

申请人： Mao-Hsiung Kuo ,  Chien-Pin Chen ,  Fa-Ming Chen

发明人： Mao-Hsiung Kuo ,  Chien-Pin Chen ,  Fa-Ming Chen

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0443 ,  G09G2310/0289 ,  G09G2310/06

摘要： A gate driver for driving a display device is disclosed. The gate driver, which includes: a first input buffer configured to for receiving a reference voltage and outputting a first buffered voltage, a control circuit configured to for outputting a plurality of scan starting signals and compensating starting signals, a plurality of compensating output buffers, and a plurality of scan output buffers. Each of the plurality of compensating output buffers is configured to respectively receive one of the compensating starting signals and respectively output a compensating signal, wherein, each compensating output buffer receives the first buffered voltage as power. Each of the plurality of scanning output buffers is configured to respectively receive one of the scan starting signals and output a scan signal.

摘要翻译： 公开了用于驱动显示装置的栅极驱动器。 所述栅极驱动器包括：第一输入缓冲器，被配置为用于接收参考电压并输出第一缓冲电压;控制电路，被配置为输出多个扫描启动信号和补偿启动信号，多个补偿输出缓冲器， 和多个扫描输出缓冲器。 多个补偿输出缓冲器中的每一个被配置为分别接收补偿起始信号之一并分别输出补偿信号，其中每个补偿输出缓冲器接收第一缓冲电压作为功率。 多个扫描输出缓冲器中的每一个被配置为分别接收扫描起始信号之一并输出扫描信号。

公开(公告)号：US08018421B2

公开(公告)日：2011-09-13

申请号：US11237826

申请日：2005-09-29

申请人： Mao-Hsiung Kuo

发明人： Mao-Hsiung Kuo

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G2330/021

摘要： A gate driver of a liquid crystal display includes classes of driving circuits coupled to each other for outputting gate pulses. At least one class of driving circuits includes a shift register and a switch. The shift register outputs the gate pulse corresponding to the class of driving circuit according to the gate pulse outputted by a former class of driving circuits. The switch controls the enable of the shift register according to the gate pulse outputted by the former class of driving circuit and the gate pulse outputted by the class of driving circuit.

摘要翻译： 液晶显示器的栅极驱动器包括彼此耦合的用于输出栅极脉冲的驱动电路。 至少一类驱动电路包括移位寄存器和开关。 移位寄存器根据由前一类驱动电路输出的门脉冲输出与驱动电路类别对应的栅极脉冲。 开关根据由前一类驱动电路输出的门脉冲和由驱动电路类别输出的门脉冲来控制移位寄存器的使能。

公开(公告)号：US07358790B2

公开(公告)日：2008-04-15

申请号：US11356707

申请日：2006-02-17

申请人： Mao-Hsiung Kuo

发明人： Mao-Hsiung Kuo

IPC分类号： H03L5/00

CPC分类号： H03K3/012 ,  H03K3/356165

摘要： A level shift circuit adds two NMOS transistors or two PMOS transistors between the NMOS transistors and PMOS transistors at the VP-side and the VN-side and connects the gates of the added transistors to the two output terminals. By this architecture, the level shift circuit of the present invention can successfully convert a small input voltage into a large output voltage with less DC current and/or without any additional bandgap circuit.

摘要翻译： 电平移位电路在VP侧和VN侧的NMOS晶体管和PMOS晶体管之间添加两个NMOS晶体管或两个PMOS晶体管，并将所加入的晶体管的栅极连接到两个输出端子。 通过这种架构，本发明的电平移位电路可以以较小的DC电流和/或没有任何附加的带隙电路成功地将小的输入电压转换成大的输出电压。

公开(公告)号：US20080062072A1

公开(公告)日：2008-03-13

申请号：US11808828

申请日：2007-06-13

申请人： Yu-Chu Yang ,  Fa-Ming Chen ,  Po-Hsien Tsai ,  Mao-Hsiung Kuo

发明人： Yu-Chu Yang ,  Fa-Ming Chen ,  Po-Hsien Tsai ,  Mao-Hsiung Kuo

IPC分类号： G09G3/20

CPC分类号： G09G3/2092 ,  G09G2320/0257 ,  G09G2330/027

摘要： A timing controller adapted to a flat display includes a voltage detecting circuit, a clock generator, a first multiplexer and a second multiplexer. The voltage detecting circuit detects a variation of an operating voltage and thus outputs a reset signal. The clock generator outputs a start signal and a first clock signal. The first multiplexer is controlled by the reset signal and coupled to the start signal and a constant voltage. The second multiplexer is controlled by the reset signal and coupled to the first clock signal and a second clock signal. A frequency of the second clock signal is obviously higher than a frequency of the first clock signal.

摘要翻译： 适于平面显示器的定时控制器包括电压检测电路，时钟发生器，第一多路复用器和第二多路复用器。 电压检测电路检测工作电压的变化，从而输出复位信号。 时钟发生器输出起始信号和第一时钟信号。 第一复用器由复位信号控制并耦合到起始信号和恒定电压。 第二复用器由复位信号控制并耦合到第一时钟信号和第二时钟信号。 第二时钟信号的频率明显高于第一时钟信号的频率。

公开(公告)号：US20060109232A1

公开(公告)日：2006-05-25

申请号：US11237826

申请日：2005-09-29

申请人： Mao-Hsiung Kuo

发明人： Mao-Hsiung Kuo

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G2330/021

摘要： A gate driver of a liquid crystal display includes classes of driving circuits coupled to each other for outputting gate pulses. At least one class of driving circuits includes a shift register and a switch. The shift register outputs the gate pulse corresponding to the class of driving circuit according to the gate pulse outputted by a former class of driving circuits. The switch controls the enable of the shift register according to the gate pulse outputted by the former class of driving circuit and the gate pulse outputted by the class of driving circuit.

摘要翻译： 液晶显示器的栅极驱动器包括彼此耦合的用于输出栅极脉冲的驱动电路。 至少一类驱动电路包括移位寄存器和开关。 移位寄存器根据由前一类驱动电路输出的门脉冲输出与驱动电路类别对应的栅极脉冲。 开关根据由前一类驱动电路输出的门脉冲和由驱动电路类别输出的门脉冲来控制移位寄存器的使能。