PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING BODY HAVING SAME
    1.
    发明申请
    PACKAGING SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND CHIP PACKAGING BODY HAVING SAME 审中-公开
    包装基板,其制造方法和具有相同的芯片包装体

    公开(公告)号:US20140036465A1

    公开(公告)日:2014-02-06

    申请号:US13863400

    申请日:2013-04-16

    Abstract: A packaging substrate includes a copper foil substrate, a sputtering copper layer, a dielectric layer, a plurality of electrically conductive connection points, and an electrically conductive pattern layer. The sputtering copper layer is formed on the copper foil substrate. The electrically conductive connection points are formed on a surface of the sputtering copper layer, which is away from the copper foil substrate. The dielectric layer is sandwiched between the electrically conductive pattern layer and the sputtering copper layer. A plurality of first blind via are formed in the first dielectric layer. The electrically conductive pattern layer includes a plurality of electrically conductive traces and a plurality of connection pads. Each electrically conductive connection point is electrically connected to the electrically conductive trace by the first blind via.

    Abstract translation: 封装基板包括铜箔基板,溅射铜层,电介质层,多个导电连接点以及导电图案层。 在铜箔基板上形成溅射铜层。 导电连接点形成在溅射铜层的远离铜箔衬底的表面上。 电介质层夹在导电图案层和溅射铜层之间。 多个第一通孔形成在第一电介质层中。 导电图案层包括多个导电迹线和多个连接焊盘。 每个导电连接点通过第一盲通孔电连接到导电迹线。

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