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7 条记录 (耗时 0.018 秒)

    Efficient configuration of daisy-chained programmable logic devices
    1.
    发明授权
    Efficient configuration of daisy-chained programmable logic devices 有权
    菊花链可编程逻辑器件的高效配置

    公开(公告)号：US07554357B2

    公开(公告)日：2009-06-30

    申请号：US11346817

    申请日：2006-02-03

    申请人： Zheng (Jeff) Chen ,  Barry Britton ,  Harold Scholz

    发明人： Zheng (Jeff) Chen ,  Barry Britton ,  Harold Scholz

    IPC分类号： H03K19/173

    CPC分类号： G06F17/5054

    摘要： In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.

    摘要翻译： 在一个实施例中，可编程逻辑器件包括：多路复用器，适于从多个外部串行接口存储器中选择压缩配置比特流; 串行接口处理器，适于通过多路复用器命令比特流选择; 以及适于将所选配置比特流解压缩为解压配置比特流的比特流解压缩器。

    Memory access via serial memory interface
    3.
    发明授权
    Memory access via serial memory interface 有权
    通过串行存储器接口进行存储器访问

    公开(公告)号：US06903574B2

    公开(公告)日：2005-06-07

    申请号：US10629512

    申请日：2003-07-29

    申请人： Zheng (Jeff) Chen ,  Fulong Zhang ,  Harold Scholz

    发明人： Zheng (Jeff) Chen ,  Fulong Zhang ,  Harold Scholz

    IPC分类号： G11C5/06 ,  H03K19/177

    CPC分类号： H03K19/17756 ,  G11C5/066 ,  H03K19/1776

    摘要： Systems and methods are disclosed herein to provide access to memory cells within a programmable logic device. For example, in accordance with an embodiment of the present invention, a serial memory interface is associated with each special functional block within a programmable logic device to provide access to configuration memory cells of the special functional block.

    摘要翻译： 本文公开的系统和方法提供对可编程逻辑器件内的存储器单元的访问。 例如，根据本发明的实施例，串行存储器接口与可编程逻辑器件内的每个特殊功能块相关联，以提供对特殊功能块的配置存储器单元的访问。

    Jitter tolerant delay-locked loop circuit
    5.
    发明授权
    Jitter tolerant delay-locked loop circuit 有权
    抖动容限延迟锁定环路

    公开(公告)号：US07620839B2

    公开(公告)日：2009-11-17

    申请号：US11302097

    申请日：2005-12-13

    申请人： Zheng (Jeff) Chen ,  Phillip Johnson ,  Fulong Zhang

    发明人： Zheng (Jeff) Chen ,  Phillip Johnson ,  Fulong Zhang

    IPC分类号： G06F1/04

    CPC分类号： G06F1/04 ,  G06F1/12

    摘要： Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.

    摘要翻译： 本文公开了系统和方法以提供改进的抖动容限延迟锁定环路。 例如，根据本发明的实施例，集成电路包括多个延迟单元，每个延迟单元具有多个可编程延迟抽头。 每个延迟单元适于提供延迟选定数量的延迟抽头的延迟时钟信号。 相位检测器适于将第一时钟信号与所选延迟时钟信号中的一个进行比较，以获得比较结果，并响应于比较结果提供多个​​控制信号。 算术逻辑单元（ALU）适于响应于由相位检测器提供的控制信号来改变选定数量的延迟抽头。

    Jitter tolerant delay-locked loop circuit
    7.
    发明申请
    Jitter tolerant delay-locked loop circuit 有权
    抖动容限延迟锁定环路

    公开(公告)号：US20070136619A1

    公开(公告)日：2007-06-14

    申请号：US11302097

    申请日：2005-12-13

    申请人： Zheng (Jeff) Chen ,  Phillip Johnson ,  Fulong Zhang

    发明人： Zheng (Jeff) Chen ,  Phillip Johnson ,  Fulong Zhang

    IPC分类号： G06F1/00

    CPC分类号： G06F1/04 ,  G06F1/12

    摘要： Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.

    摘要翻译： 本文公开了系统和方法以提供改进的抖动容限延迟锁定环路。 例如，根据本发明的实施例，集成电路包括多个延迟单元，每个延迟单元具有多个可编程延迟抽头。 每个延迟单元适于提供延迟选定数量的延迟抽头的延迟时钟信号。 相位检测器适于将第一时钟信号与所选延迟时钟信号中的一个进行比较，以获得比较结果，并响应于比较结果提供多个​​控制信号。 算术逻辑单元（ALU）适于响应于由相位检测器提供的控制信号来改变选定数量的延迟抽头。